2021-10-24 19:02:30 +00:00
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-21 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file Media Access Controller for Ethernet (MACE) definitions. */
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#ifndef MACE_H
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#define MACE_H
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#include <cinttypes>
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// MACE Chip ID from AMD datasheet
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// TODO: compare with real HW
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#define MACE_ID 0x3940
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// MACE registers offsets
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// Refer to the Am79C940 datasheet for details
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2022-03-09 17:03:58 +00:00
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namespace MaceEnet {
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2021-10-24 19:02:30 +00:00
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enum MaceReg : uint8_t {
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Rcv_FIFO = 0,
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Xmit_FIFO = 1,
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Xmit_Frame_Ctrl = 2,
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Xmit_Frame_Stat = 3,
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Xmit_Retry_Cnt = 4,
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Rcv_Frame_Ctrl = 5,
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Rcv_Frame_Stat = 6,
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FIFO_Frame_Cnt = 7,
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Interrupt = 8,
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Interrupt_Mask = 9,
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Poll = 0x0A,
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BIU_Config_Ctrl = 0x0B,
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FIFO_Config = 0x0C,
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MAC_Config_Ctrl = 0x0D,
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PLS_Config_Ctrl = 0x0E,
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PHY_Config_Ctrl = 0x0F,
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Chip_ID_Lo = 0x10,
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Chip_ID_Hi = 0x11,
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Addr_Config = 0x12,
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Log_Addr_Flt = 0x14,
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Phys_Addr = 0x15,
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Missed_Pkt_Cnt = 0x18,
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Runt_Pkt_Cnt = 0x1A, // not used in Macintosh?
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Rcv_Collis_Cnt = 0x1B, // not used in Macintosh?
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User_Test = 0x1D,
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Rsrvd_Test_1 = 0x1E, // not used in Macintosh?
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Rsrvd_Test_2 = 0x1F, // not used in Macintosh?
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};
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2022-03-09 17:03:58 +00:00
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}; // namespace MaceEnet
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2021-10-24 19:02:30 +00:00
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class MaceController {
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public:
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MaceController(uint16_t id) { this->chip_id = id; };
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~MaceController() = default;
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// MACE registers access
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uint8_t read(uint8_t reg_offset);
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void write(uint8_t reg_offset, uint8_t value);
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private:
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uint16_t chip_id; // per-instance MACE Chip ID
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};
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#endif // MACE_H
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