2022-01-17 12:57:01 +00:00
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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2024-02-09 08:49:33 +00:00
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Copyright (C) 2018-24 divingkatae and maximum
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2022-01-17 12:57:01 +00:00
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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2022-06-09 21:16:03 +00:00
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/** Platinum Memory/Display Controller emulation. */
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2022-01-17 12:57:01 +00:00
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2024-02-09 08:49:33 +00:00
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#include <core/timermanager.h>
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2022-07-17 03:35:17 +00:00
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#include <devices/deviceregistry.h>
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2024-02-09 08:49:33 +00:00
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#include <devices/ioctrl/macio.h>
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2022-06-09 21:16:03 +00:00
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#include <devices/memctrl/platinum.h>
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#include <devices/video/displayid.h>
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2022-01-17 12:57:01 +00:00
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#include <loguru.hpp>
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2024-02-09 08:49:33 +00:00
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#include <machines/machinebase.h>
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#include <memaccess.h>
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2022-01-17 12:57:01 +00:00
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#include <cinttypes>
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using namespace Platinum;
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2024-02-09 08:49:33 +00:00
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PlatinumCtrl::PlatinumCtrl() : MemCtrlBase(), VideoCtrlBase(640, 480) {
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set_name("Platinum");
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2022-01-17 12:57:01 +00:00
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2022-07-17 03:35:17 +00:00
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supports_types(HWCompType::MEM_CTRL | HWCompType::MMIO_DEV);
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2024-02-09 08:49:33 +00:00
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// add MMIO region for VRAM
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add_mmio_region(VRAM_REGION_BASE, 0x01000000, this);
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2022-01-17 12:57:01 +00:00
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// add MMIO region for the configuration and status registers
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2024-02-09 08:49:33 +00:00
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add_mmio_region(PLATINUM_IOREG_BASE, 0x500, this);
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2022-01-17 12:57:01 +00:00
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2024-02-09 08:49:33 +00:00
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// get VRAM size
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this->vram_megs = GET_INT_PROP("gfxmem_size");
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this->vram_size = this->vram_megs << 20;
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2022-06-09 21:16:03 +00:00
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2024-02-09 08:49:33 +00:00
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// enable half bank access if 1MB VRAM + FB_CONFIG_1[CFG1_FULL_BANKS] = 1
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this->half_bank = !!(this->vram_megs == 1);
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this->half_access = 0;
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// allocate VRAM
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this->vram_ptr = std::unique_ptr<uint8_t[]> (new uint8_t[this->vram_size]);
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2022-06-09 21:16:03 +00:00
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2022-01-17 12:57:01 +00:00
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// initialize the CPUID register with the following CPU:
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2024-02-09 08:49:33 +00:00
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// PowerPC 601 @ 90 MHz, bus frequency: 45 MHz
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this->cpu_id = (0x3001 << 16) | ClkSrc2 | (CpuSpeed2::CPU_90_BUS_45 << 8);
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2022-06-09 21:16:03 +00:00
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this->display_id = std::unique_ptr<DisplayID> (new DisplayID());
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2024-02-09 08:49:33 +00:00
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// attach DACula RAMDAC
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this->dacula = std::unique_ptr<AppleRamdac>(new AppleRamdac(DacFlavour::DACULA));
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this->dacula->set_clut_entry_cb = [this](uint8_t index, uint8_t *colors) {
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this->set_palette_color(index, colors[0], colors[1], colors[2], 0xFF);
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};
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this->dacula->cursor_ctrl_cb = [this](bool cursor_on) {
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if (cursor_on) {
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2024-02-19 01:22:04 +00:00
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this->dacula->measure_hw_cursor(this->fb_ptr - 16);
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2024-02-09 08:49:33 +00:00
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this->cursor_ovl_cb = [this](uint8_t *dst_buf, int dst_pitch) {
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2024-02-19 01:22:04 +00:00
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this->dacula->draw_hw_cursor(this->fb_ptr - 16,
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2024-02-09 08:49:33 +00:00
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dst_buf, dst_pitch);
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};
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} else {
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this->cursor_ovl_cb = nullptr;
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}
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};
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2022-01-17 12:57:01 +00:00
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}
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2024-02-09 08:49:33 +00:00
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int PlatinumCtrl::device_postinit() {
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// register DACula with the I/O controller as IOBus Device #2
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GrandCentral* gc_obj = dynamic_cast<GrandCentral*>(gMachineObj->get_comp_by_name("GrandCentral"));
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gc_obj->attach_iodevice(1, this->dacula.get());
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this->int_ctrl = dynamic_cast<InterruptCtrl*>(
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gMachineObj->get_comp_by_type(HWCompType::INT_CTRL));
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2024-02-11 23:54:44 +00:00
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this->irq_id = this->int_ctrl->register_dev_int(IntSrc::PLATINUM);
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2024-02-09 08:49:33 +00:00
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this->vbl_cb = [this](uint8_t irq_line_state) {
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this->update_irq(irq_line_state, SWATCH_INT_VBL);
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};
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return 0;
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}
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uint32_t PlatinumCtrl::read(uint32_t rgn_start, uint32_t offset, int size) {
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if (rgn_start == VRAM_REGION_BASE) {
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if (offset < this->vram_size) {
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// HACK: half bank configurations should return invalid data
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// for the lower DWORD (in the PPC order!) to be recognized.
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// The simplest way to achieve that is to redirect access
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// to the upper DWORD by setting bit 2 of the address.
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if (this->half_access)
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offset |= 4;
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return read_mem(&this->vram_ptr[offset], size);
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} else {
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LOG_F(WARNING, "%s: read from unmapped aperture address 0x%X",
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this->name.c_str(), this->fb_addr + offset);
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return (uint32_t)-1;
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}
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}
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2024-02-15 14:35:17 +00:00
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// non-DWORD accesses will produce undefined results according with the ERS
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// I believe we can safely return 0 in this case
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if (size != 4)
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2022-01-17 12:57:01 +00:00
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return 0;
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switch (offset) {
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case PlatinumReg::CPU_ID:
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return this->cpu_id;
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2022-03-21 14:04:07 +00:00
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case PlatinumReg::DRAM_REFRESH:
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return this->dram_refresh;
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case PlatinumReg::BANK_0_BASE:
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case PlatinumReg::BANK_1_BASE:
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case PlatinumReg::BANK_2_BASE:
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case PlatinumReg::BANK_3_BASE:
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case PlatinumReg::BANK_4_BASE:
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case PlatinumReg::BANK_5_BASE:
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case PlatinumReg::BANK_6_BASE:
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case PlatinumReg::BANK_7_BASE:
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return this->bank_base[(offset - PlatinumReg::BANK_0_BASE) >> 4];
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case PlatinumReg::CACHE_CONFIG:
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return 0; // report no L2 cache installed
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2022-06-09 21:16:03 +00:00
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case PlatinumReg::FB_BASE_ADDR:
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return this->fb_addr;
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case PlatinumReg::MON_ID_SENSE:
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2024-02-09 08:49:33 +00:00
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return (this->mon_sense ^ 7);
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case PlatinumReg::SWATCH_CONFIG:
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return this->swatch_config;
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case PlatinumReg::SWATCH_INT_STAT:
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return this->swatch_int_stat;
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case PlatinumReg::CLR_CURSOR_INT:
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this->update_irq(0, SWATCH_INT_CURSOR);
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return 0;
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2024-02-19 01:28:33 +00:00
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//case PlatinumReg::CLR_ANIM_INT:
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//case PlatinumReg::CLR_VBL_INT:
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//case PlatinumReg::CURSOR_LINE:
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//case PlatinumReg::ANIMATE_LINE:
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//case PlatinumReg::COUNTER_TEST:
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//break;
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case PlatinumReg::SWATCH_HSERR:
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case PlatinumReg::SWATCH_HLFLN:
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case PlatinumReg::SWATCH_HEQ:
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case PlatinumReg::SWATCH_HSP:
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case PlatinumReg::SWATCH_HBWAY:
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case PlatinumReg::SWATCH_HBRST:
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case PlatinumReg::SWATCH_HBP:
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case PlatinumReg::SWATCH_HAL:
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case PlatinumReg::SWATCH_HFP:
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case PlatinumReg::SWATCH_HPIX:
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case PlatinumReg::SWATCH_VHLINE:
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case PlatinumReg::SWATCH_VSYNC:
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case PlatinumReg::SWATCH_VBPEQ:
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case PlatinumReg::SWATCH_VBP:
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case PlatinumReg::SWATCH_VAL:
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case PlatinumReg::SWATCH_VFP:
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case PlatinumReg::SWATCH_VFPEQ:
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return this->swatch_params[REG_TO_INDEX(offset >> 4)];
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2024-02-09 08:49:33 +00:00
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case PlatinumReg::TIMING_ADJUST:
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return this->timing_adjust;
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case PlatinumReg::IRIDIUM_CONFIG:
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return this->iridium_cfg;
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2022-01-17 12:57:01 +00:00
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default:
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2024-02-09 08:49:33 +00:00
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LOG_F(WARNING, "%s: unknown register read at offset 0x%X", this->name.c_str(),
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offset);
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2022-01-17 12:57:01 +00:00
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}
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return 0;
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}
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2022-03-21 14:04:07 +00:00
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void PlatinumCtrl::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
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2022-01-17 12:57:01 +00:00
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{
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2024-02-21 14:07:18 +00:00
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static uint8_t vid_enable_seq[] = {3, 2, 0};
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2024-02-09 08:49:33 +00:00
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if (rgn_start == VRAM_REGION_BASE) {
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if (offset < this->vram_size)
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write_mem(&this->vram_ptr[offset], value, size);
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else
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LOG_F(WARNING, "%s: write to unmapped aperture address 0x%X",
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this->name.c_str(), this->fb_addr + offset);
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return;
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}
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2024-02-15 14:35:17 +00:00
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if (size != 4) {
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LOG_F(WARNING, "%s: non-DWORD write access, size %d!", this->name.c_str(),
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size);
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return;
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}
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2022-03-21 14:04:07 +00:00
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switch (offset) {
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case PlatinumReg::ROM_TIMING:
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this->rom_timing = value;
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break;
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case PlatinumReg::DRAM_TIMING:
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this->dram_timing = value;
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break;
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case PlatinumReg::DRAM_REFRESH:
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this->dram_refresh = value;
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break;
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case PlatinumReg::BANK_0_BASE:
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case PlatinumReg::BANK_1_BASE:
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case PlatinumReg::BANK_2_BASE:
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case PlatinumReg::BANK_3_BASE:
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case PlatinumReg::BANK_4_BASE:
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case PlatinumReg::BANK_5_BASE:
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case PlatinumReg::BANK_6_BASE:
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case PlatinumReg::BANK_7_BASE:
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this->bank_base[(offset - PlatinumReg::BANK_0_BASE) >> 4] = value;
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break;
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2022-06-09 21:16:03 +00:00
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case PlatinumReg::FB_BASE_ADDR:
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2024-02-09 08:49:33 +00:00
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this->fb_addr = value;
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this->fb_offset = value & 0x3FFFFF;
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break;
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case PlatinumReg::ROW_WORDS:
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this->row_words = value & ~7;
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break;
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case PlatinumReg::CLOCK_DIVISOR:
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this->clock_divisor = value;
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2022-06-09 21:16:03 +00:00
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break;
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case PlatinumReg::FB_CONFIG_1:
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this->fb_config_1 = value;
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2024-02-09 08:49:33 +00:00
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this->half_bank = !!(this->vram_megs == 1 && (value & CFG1_FULL_BANKS));
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2022-06-09 21:16:03 +00:00
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break;
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case PlatinumReg::FB_CONFIG_2:
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this->fb_config_2 = value;
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break;
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case PlatinumReg::VMEM_PAGE_MODE:
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this->vmem_fp_mode = value;
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break;
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case PlatinumReg::MON_ID_SENSE:
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2024-02-09 08:49:33 +00:00
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value &= 7;
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this->mon_sense = this->display_id->read_monitor_sense(value, value ^ 7)
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<< (value ^ 7);
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2022-06-09 21:16:03 +00:00
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break;
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case PlatinumReg::FB_RESET:
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2024-02-09 08:49:33 +00:00
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if (value == 7 && this->crtc_on) {
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LOG_F(INFO, "%s: video disabled", this->name.c_str());
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this->reset_step = 0;
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} else if (value == vid_enable_seq[this->reset_step]) {
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if (++this->reset_step >= 3) {
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if (this->fb_config_1 & CFG1_VID_ENABLE) {
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LOG_F(INFO, "%s: video enabled", this->name.c_str());
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this->enable_display();
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} else {
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this->blank_display();
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}
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this->reset_step = 0;
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}
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} else
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this->reset_step = 0;
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2022-06-09 21:16:03 +00:00
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this->fb_reset = value;
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2024-02-09 08:49:33 +00:00
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this->half_access = !!(this->half_bank && value == 6);
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2022-06-09 21:16:03 +00:00
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break;
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case PlatinumReg::VRAM_REFRESH:
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this->vram_refresh = value;
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break;
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case PlatinumReg::SWATCH_CONFIG:
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this->swatch_config = value;
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break;
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case PlatinumReg::SWATCH_INT_MASK:
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this->swatch_int_mask = value;
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2024-02-09 08:49:33 +00:00
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if (this->swatch_int_mask & SWATCH_INT_VBL)
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LOG_F(INFO, "%s: VBL interrupt enabled", this->name.c_str());
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2022-06-09 21:16:03 +00:00
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break;
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2024-02-09 08:49:33 +00:00
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case PlatinumReg::CURSOR_LINE:
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this->cursor_line = value;
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if (this->swatch_int_mask & SWATCH_INT_CURSOR)
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this->enable_cursor_int();
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2022-06-09 21:16:03 +00:00
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break;
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2024-02-09 08:49:33 +00:00
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case PlatinumReg::SWATCH_HSERR:
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case PlatinumReg::SWATCH_HLFLN:
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case PlatinumReg::SWATCH_HEQ:
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case PlatinumReg::SWATCH_HSP:
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case PlatinumReg::SWATCH_HBWAY:
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case PlatinumReg::SWATCH_HBRST:
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case PlatinumReg::SWATCH_HBP:
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case PlatinumReg::SWATCH_HAL:
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2022-06-09 21:16:03 +00:00
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case PlatinumReg::SWATCH_HFP:
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case PlatinumReg::SWATCH_HPIX:
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2024-02-09 08:49:33 +00:00
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case PlatinumReg::SWATCH_VHLINE:
|
|
|
|
case PlatinumReg::SWATCH_VSYNC:
|
|
|
|
case PlatinumReg::SWATCH_VBPEQ:
|
|
|
|
case PlatinumReg::SWATCH_VBP:
|
2022-06-09 21:16:03 +00:00
|
|
|
case PlatinumReg::SWATCH_VAL:
|
|
|
|
case PlatinumReg::SWATCH_VFP:
|
2024-02-09 08:49:33 +00:00
|
|
|
case PlatinumReg::SWATCH_VFPEQ:
|
|
|
|
this->swatch_params[REG_TO_INDEX(offset)] = value;
|
|
|
|
break;
|
|
|
|
case PlatinumReg::TIMING_ADJUST:
|
|
|
|
this->timing_adjust = value;
|
|
|
|
break;
|
|
|
|
case PlatinumReg::IRIDIUM_CONFIG:
|
|
|
|
if (!(value & 1))
|
2024-02-19 01:24:37 +00:00
|
|
|
LOG_F(ERROR, "%s: little-endian system bus is not implemented", this->name.c_str());
|
2024-02-09 08:49:33 +00:00
|
|
|
this->iridium_cfg = (this->iridium_cfg & ~7) | (value & 7);
|
2022-06-09 21:16:03 +00:00
|
|
|
break;
|
2022-03-21 14:04:07 +00:00
|
|
|
default:
|
2024-02-09 08:49:33 +00:00
|
|
|
LOG_F(WARNING, "%s: unknown register write at offset 0x%X", this->name.c_str(),
|
|
|
|
offset);
|
2022-03-21 14:04:07 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2024-02-09 08:49:33 +00:00
|
|
|
void PlatinumCtrl::insert_ram_dimm(int slot_num, uint32_t capacity) {
|
2022-03-21 14:04:07 +00:00
|
|
|
if (slot_num < 0 || slot_num >= 4) {
|
2024-02-09 08:49:33 +00:00
|
|
|
ABORT_F("%s: invalid DIMM slot %d", this->name.c_str(), slot_num);
|
2022-03-21 14:04:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
switch (capacity) {
|
|
|
|
case DRAM_CAP_2MB:
|
|
|
|
case DRAM_CAP_4MB:
|
|
|
|
case DRAM_CAP_8MB:
|
|
|
|
case DRAM_CAP_16MB:
|
|
|
|
case DRAM_CAP_32MB:
|
|
|
|
case DRAM_CAP_64MB:
|
|
|
|
this->bank_size[slot_num * 2 + 0] = capacity;
|
|
|
|
break;
|
|
|
|
case DRAM_CAP_128MB:
|
|
|
|
this->bank_size[slot_num * 2 + 0] = DRAM_CAP_64MB;
|
|
|
|
this->bank_size[slot_num * 2 + 1] = DRAM_CAP_64MB;
|
|
|
|
break;
|
|
|
|
default:
|
2024-02-09 08:49:33 +00:00
|
|
|
ABORT_F("%s: unsupported DRAM capacity %d", this->name.c_str(), capacity);
|
2022-03-21 14:04:07 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2024-02-09 08:49:33 +00:00
|
|
|
void PlatinumCtrl::map_phys_ram() {
|
2022-03-21 14:04:07 +00:00
|
|
|
uint32_t total_ram = 0;
|
|
|
|
|
|
|
|
for (int i = 0; i < 8; i++) {
|
|
|
|
total_ram += this->bank_size[i];
|
|
|
|
}
|
|
|
|
|
|
|
|
if (total_ram > DRAM_CAP_64MB) {
|
2024-02-09 08:49:33 +00:00
|
|
|
ABORT_F("%s: RAM bigger than 64MB not supported yet", this->name.c_str());
|
2022-03-21 14:04:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!add_ram_region(0x00000000, total_ram)) {
|
2024-02-09 08:49:33 +00:00
|
|
|
ABORT_F("%s: could not allocate RAM storage", this->name.c_str());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// ====================== Framebuffer controller stuff =======================
|
|
|
|
void PlatinumCtrl::enable_display() {
|
|
|
|
int clock_divisor = this->dacula->get_clock_div();
|
|
|
|
|
|
|
|
this->pixel_clock = this->dacula->get_dot_freq();
|
|
|
|
|
|
|
|
// calculate active_width and active_height from Swatch parameters
|
|
|
|
int new_width = swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_HFP)] -
|
|
|
|
swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_HAL)];
|
|
|
|
int new_height = swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_VFP)] -
|
|
|
|
swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_VAL)];
|
|
|
|
|
|
|
|
this->hori_blank = swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_HAL)] +
|
|
|
|
(swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_HSP)] -
|
|
|
|
swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_HFP)]);
|
|
|
|
|
|
|
|
new_width *= clock_divisor;
|
|
|
|
this->hori_blank *= clock_divisor;
|
|
|
|
|
|
|
|
this->vert_blank = swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_VAL)] +
|
|
|
|
(swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_VSYNC)] -
|
|
|
|
swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_VFP)]);
|
|
|
|
|
|
|
|
if (!(this->fb_config_1 & CFG1_INTERLACE)) {
|
|
|
|
new_height >>= 1;
|
|
|
|
this->vert_blank >>= 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
this->active_width = new_width;
|
|
|
|
this->active_height = new_height;
|
|
|
|
|
|
|
|
this->hori_total = this->hori_blank + new_width;
|
|
|
|
this->vert_total = this->vert_blank + new_height;
|
|
|
|
|
|
|
|
// set framebuffer parameters
|
2024-02-19 01:21:14 +00:00
|
|
|
this->fb_ptr = &this->vram_ptr[this->fb_offset] + 16;
|
2024-02-09 08:49:33 +00:00
|
|
|
this->fb_pitch = this->row_words;
|
|
|
|
|
|
|
|
this->pixel_depth = this->dacula->get_pix_width();
|
|
|
|
|
|
|
|
// attach framebuffer conversion routine
|
|
|
|
switch (this->pixel_depth) {
|
|
|
|
case 8:
|
|
|
|
this->convert_fb_cb = [this](uint8_t *dst_buf, int dst_pitch) {
|
|
|
|
this->convert_frame_8bpp_indexed(dst_buf, dst_pitch);
|
|
|
|
};
|
|
|
|
break;
|
|
|
|
case 16:
|
|
|
|
this->convert_fb_cb = [this](uint8_t *dst_buf, int dst_pitch) {
|
|
|
|
this->convert_frame_15bpp_BE(dst_buf, dst_pitch);
|
|
|
|
};
|
|
|
|
break;
|
|
|
|
case 32:
|
|
|
|
this->convert_fb_cb = [this](uint8_t *dst_buf, int dst_pitch) {
|
|
|
|
this->convert_frame_32bpp_BE(dst_buf, dst_pitch);
|
|
|
|
};
|
|
|
|
break;
|
|
|
|
default:
|
2024-02-19 01:24:37 +00:00
|
|
|
LOG_F(ERROR, "%s: invalid pixel width %d", this->name.c_str(), this->pixel_depth);
|
2024-02-09 08:49:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
this->dacula->set_fb_parameters(this->active_width, this->active_height, this->fb_pitch);
|
|
|
|
|
|
|
|
this->stop_refresh_task();
|
|
|
|
|
|
|
|
this->refresh_rate = (double)(this->pixel_clock) / (this->hori_total * this->vert_total);
|
|
|
|
this->start_refresh_task();
|
|
|
|
|
|
|
|
LOG_F(INFO, "%s: video width=%d, height=%d", this->name.c_str(), new_width, new_height);
|
|
|
|
LOG_F(INFO, "%s: refresh rate set to %f Hz", this->name.c_str(), this->refresh_rate);
|
|
|
|
|
|
|
|
this->blank_on = false;
|
|
|
|
this->crtc_on = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
void PlatinumCtrl::enable_cursor_int() {
|
|
|
|
if (!(this->swatch_int_mask & SWATCH_INT_CURSOR))
|
|
|
|
return;
|
|
|
|
|
|
|
|
uint64_t cursor_int_freq = static_cast<uint64_t>((1.0f / (double)this->pixel_clock) *
|
|
|
|
this->hori_total * this->cursor_line * NS_PER_SEC + 0.5f);
|
|
|
|
LOG_F(INFO, "%s: cursor interrupt frequency %lld ns", this->name.c_str(),
|
|
|
|
cursor_int_freq);
|
|
|
|
|
|
|
|
if (this->cursor_task_id)
|
|
|
|
TimerManager::get_instance()->cancel_timer(this->cursor_task_id);
|
|
|
|
|
|
|
|
this->cursor_task_id = TimerManager::get_instance()->add_cyclic_timer(
|
|
|
|
cursor_int_freq,
|
|
|
|
[this]() {
|
|
|
|
this->update_irq(1, SWATCH_INT_CURSOR); // generate cursor interrupt
|
|
|
|
}
|
|
|
|
);
|
|
|
|
}
|
|
|
|
|
|
|
|
void PlatinumCtrl::update_irq(uint8_t irq_line_state, uint8_t irq_mask) {
|
|
|
|
if (irq_line_state != !!(this->swatch_int_stat & irq_mask)) {
|
|
|
|
if (irq_line_state)
|
|
|
|
this->swatch_int_stat |= irq_mask;
|
|
|
|
else
|
|
|
|
this->swatch_int_stat &= ~irq_mask;
|
|
|
|
|
|
|
|
if (this->swatch_int_mask & irq_mask)
|
|
|
|
this->int_ctrl->ack_int(this->irq_id, irq_line_state);
|
2022-03-21 14:04:07 +00:00
|
|
|
}
|
2022-01-17 12:57:01 +00:00
|
|
|
}
|
2022-07-17 03:35:17 +00:00
|
|
|
|
2024-02-09 08:49:33 +00:00
|
|
|
// ========================== Device registry stuff ==========================
|
|
|
|
static const PropMap Platinum_Properties = {
|
|
|
|
{"gfxmem_size",
|
|
|
|
new IntProperty(1, vector<uint32_t>({1, 2, 4}))},
|
|
|
|
{"mon_id",
|
|
|
|
new StrProperty("HiRes12-14in")},
|
|
|
|
};
|
|
|
|
|
2022-07-17 03:35:17 +00:00
|
|
|
static const DeviceDescription Platinum_Descriptor = {
|
2024-02-09 08:49:33 +00:00
|
|
|
PlatinumCtrl::create, {}, Platinum_Properties
|
2022-07-17 03:35:17 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
REGISTER_DEVICE(Platinum, Platinum_Descriptor);
|