2021-12-12 20:40:04 +00:00
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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2022-02-06 14:23:30 +00:00
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Copyright (C) 2018-22 divingkatae and maximum
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2021-12-12 20:40:04 +00:00
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file Sander-Wozniak Machine 3 (SWIM3) emulation. */
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2022-02-07 17:42:35 +00:00
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#include <core/timermanager.h>
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2022-07-11 22:59:54 +00:00
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#include <devices/deviceregistry.h>
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2022-02-07 22:04:13 +00:00
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#include <devices/common/hwinterrupt.h>
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2022-02-06 14:23:30 +00:00
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#include <devices/floppy/superdrive.h>
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#include <devices/floppy/swim3.h>
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2021-12-12 20:40:04 +00:00
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#include <loguru.hpp>
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2022-02-06 14:23:30 +00:00
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#include <machines/machinebase.h>
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2022-07-11 22:59:54 +00:00
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#include <machines/machineproperties.h>
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2021-12-12 20:40:04 +00:00
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#include <cinttypes>
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#include <memory>
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2022-07-11 22:59:54 +00:00
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#include <string>
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2022-09-03 22:20:29 +00:00
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#include <vector>
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2021-12-12 20:40:04 +00:00
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using namespace Swim3;
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Swim3Ctrl::Swim3Ctrl()
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{
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2022-02-07 22:04:13 +00:00
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this->name = "SWIM3";
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this->supported_types = HWCompType::FLOPPY_CTRL;
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2021-12-12 20:40:04 +00:00
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this->setup_reg = 0;
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this->mode_reg = 0;
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this->int_reg = 0;
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2022-02-07 17:42:35 +00:00
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this->int_flags = 0;
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2021-12-12 20:40:04 +00:00
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this->int_mask = 0;
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2022-02-13 02:07:32 +00:00
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this->error = 0;
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2021-12-12 20:40:04 +00:00
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this->xfer_cnt = 0;
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this->first_sec = 0xFF;
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2022-11-17 13:17:25 +00:00
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this->cur_state = SWIM3_IDLE;
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2021-12-12 20:40:04 +00:00
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// Attach virtual Superdrive to the internal drive connector
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// TODO: make SWIM3/drive wiring user selectable
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this->int_drive = std::unique_ptr<MacSuperdrive::MacSuperDrive>
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(new MacSuperdrive::MacSuperDrive());
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}
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2022-02-07 22:04:13 +00:00
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int Swim3Ctrl::device_postinit()
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{
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this->int_ctrl = dynamic_cast<InterruptCtrl*>(
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gMachineObj->get_comp_by_type(HWCompType::INT_CTRL));
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this->irq_id = this->int_ctrl->register_dev_int(IntSrc::SWIM3);
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2022-07-11 22:59:54 +00:00
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// if a floppy image was given "insert" it into the virtual superdrive
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std::string fd_image_path = GET_STR_PROP("fdd_img");
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2022-07-19 21:48:17 +00:00
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int fd_write_prot = GET_BIN_PROP("fdd_wr_prot");
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2022-07-11 22:59:54 +00:00
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if (!fd_image_path.empty()) {
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2022-07-19 21:48:17 +00:00
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this->int_drive->insert_disk(fd_image_path, fd_write_prot);
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2022-07-11 22:59:54 +00:00
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}
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2022-02-07 22:04:13 +00:00
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return 0;
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};
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2021-12-12 20:40:04 +00:00
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uint8_t Swim3Ctrl::read(uint8_t reg_offset)
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{
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2022-11-17 13:17:25 +00:00
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uint8_t status_addr, rddata_val, old_int_flags, old_error;
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2021-12-12 20:40:04 +00:00
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switch(reg_offset) {
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2022-11-17 17:02:53 +00:00
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case Swim3Reg::Timer:
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return this->calc_timer_val();
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2022-02-13 02:07:32 +00:00
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case Swim3Reg::Error:
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old_error = this->error;
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this->error = 0;
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return old_error;
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2021-12-12 20:40:04 +00:00
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case Swim3Reg::Phase:
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return this->phase_lines;
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case Swim3Reg::Setup:
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return this->setup_reg;
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case Swim3Reg::Handshake_Mode1:
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if (this->mode_reg & 2) { // internal drive?
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status_addr = ((this->mode_reg & 0x20) >> 2) | (this->phase_lines & 7);
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2022-11-17 13:17:25 +00:00
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rddata_val = this->int_drive->status(status_addr) & 1;
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2022-07-11 22:59:54 +00:00
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2022-11-17 13:17:25 +00:00
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// transfer rddata_val to both bit 2 (RDDATA) and bit 3 (SENSE)
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2022-07-11 22:59:54 +00:00
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// because those signals seem to be historically wired together
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2022-11-17 13:17:25 +00:00
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return (rddata_val << 2) | (rddata_val << 3);
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2021-12-12 20:40:04 +00:00
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}
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2022-11-17 13:17:25 +00:00
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return 0xC; // report both RdData & Sense high
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2022-02-07 17:42:35 +00:00
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case Swim3Reg::Interrupt_Flags:
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old_int_flags = this->int_flags;
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this->int_flags = 0; // read from this register clears all flags
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update_irq();
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return old_int_flags;
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2022-02-13 02:07:32 +00:00
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case Swim3Reg::Current_Track:
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return this->cur_track;
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case Swim3Reg::Current_Sector:
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return this->cur_sector;
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case Swim3Reg::Gap_Format:
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return this->format;
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case Swim3Reg::First_Sector:
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return this->first_sec;
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case Swim3Reg::Sectors_To_Xfer:
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return this->xfer_cnt;
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2022-02-07 17:42:35 +00:00
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case Swim3Reg::Interrupt_Mask:
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return this->int_mask;
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2021-12-12 20:40:04 +00:00
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default:
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LOG_F(INFO, "SWIM3: reading from 0x%X register", reg_offset);
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}
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return 0;
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}
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void Swim3Ctrl::write(uint8_t reg_offset, uint8_t value)
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{
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2022-11-17 13:17:25 +00:00
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uint8_t old_mode_reg, status_addr;
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2022-02-07 17:42:35 +00:00
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2021-12-12 20:40:04 +00:00
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switch(reg_offset) {
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2022-11-17 13:17:25 +00:00
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case Swim3Reg::Timer:
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2022-11-17 17:02:53 +00:00
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this->init_timer(value);
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2022-11-17 13:17:25 +00:00
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break;
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2021-12-12 20:40:04 +00:00
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case Swim3Reg::Param_Data:
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this->pram = value;
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break;
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case Swim3Reg::Phase:
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this->phase_lines = value & 0xF;
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2022-11-17 13:17:25 +00:00
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if (this->phase_lines & 8) { // CA3 aka LSTRB high -> sending a command to the drive
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if (this->mode_reg & 2) { // if internal drive is selected
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2021-12-12 20:40:04 +00:00
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this->int_drive->command(
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((this->mode_reg & 0x20) >> 3) | (this->phase_lines & 3),
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(value >> 2) & 1
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);
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}
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2022-11-17 13:17:25 +00:00
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} else if (this->phase_lines == 4 && (this->mode_reg & 2)) {
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status_addr = ((this->mode_reg & 0x20) >> 2) | (this->phase_lines & 7);
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this->rd_line = this->int_drive->status(status_addr) & 1;
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2021-12-12 20:40:04 +00:00
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}
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break;
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case Swim3Reg::Setup:
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this->setup_reg = value;
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break;
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case Swim3Reg::Status_Mode0:
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// ones in value clear the corresponding bits in the mode register
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2022-02-07 17:42:35 +00:00
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if ((this->mode_reg & value) & (SWIM3_GO | SWIM3_GO_STEP)) {
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if (value & SWIM3_GO_STEP) {
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stop_stepping();
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} else {
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2022-02-13 02:07:32 +00:00
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stop_disk_access();
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2022-02-07 17:42:35 +00:00
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}
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}
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2021-12-12 20:40:04 +00:00
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this->mode_reg &= ~value;
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break;
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case Swim3Reg::Handshake_Mode1:
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// ones in value set the corresponding bits in the mode register
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2022-02-07 17:42:35 +00:00
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if ((this->mode_reg ^ value) & (SWIM3_GO | SWIM3_GO_STEP)) {
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if (value & SWIM3_GO_STEP) {
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start_stepping();
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} else {
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2022-02-13 02:07:32 +00:00
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start_disk_access();
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2022-02-07 17:42:35 +00:00
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}
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}
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2021-12-12 20:40:04 +00:00
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this->mode_reg |= value;
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break;
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2022-02-07 17:42:35 +00:00
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case Swim3Reg::Step:
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this->step_count = value;
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break;
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2022-02-13 02:07:32 +00:00
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case Swim3Reg::Gap_Format:
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this->gap_size = value;
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break;
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case Swim3Reg::First_Sector:
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this->first_sec = value;
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break;
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case Swim3Reg::Sectors_To_Xfer:
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this->xfer_cnt = value;
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break;
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2021-12-12 20:40:04 +00:00
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case Swim3Reg::Interrupt_Mask:
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this->int_mask = value;
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break;
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default:
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LOG_F(INFO, "SWIM3: writing 0x%X to register 0x%X", value, reg_offset);
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}
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}
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2022-02-07 17:42:35 +00:00
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void Swim3Ctrl::update_irq()
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{
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2022-02-14 22:06:07 +00:00
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if (this->mode_reg & SWIM3_INT_ENA) {
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uint8_t new_irq = !!(this->int_flags & this->int_mask);
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if (new_irq != this->irq) {
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this->irq = new_irq;
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this->int_ctrl->ack_int(this->irq_id, new_irq);
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}
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2022-02-07 22:04:13 +00:00
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}
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2022-02-07 17:42:35 +00:00
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}
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void Swim3Ctrl::do_step()
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{
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if (this->mode_reg & SWIM3_GO_STEP && this->step_count) { // are we still stepping?
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// instruct the drive to perform single step in current direction
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this->int_drive->command(MacSuperdrive::CommandAddr::Do_Step, 0);
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if (--this->step_count == 0) {
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if (this->step_timer_id) {
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this->stop_stepping();
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}
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this->int_flags |= INT_STEP_DONE;
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update_irq();
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}
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}
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}
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void Swim3Ctrl::start_stepping()
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{
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if (!this->step_count) {
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LOG_F(WARNING, "SWIM3: step_count is zero while go_step is active!");
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return;
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}
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2022-02-13 02:07:32 +00:00
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if (this->mode_reg & SWIM3_GO_STEP || this->step_timer_id) {
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LOG_F(ERROR, "SWIM3: another stepping action is running!");
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return;
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}
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if (this->mode_reg & SWIM3_GO || this->access_timer_id) {
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LOG_F(ERROR, "SWIM3: stepping attempt while disk access is in progress!");
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return;
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}
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2022-02-07 17:42:35 +00:00
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if ((((this->mode_reg & 0x20) >> 3) | (this->phase_lines & 3))
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!= MacSuperdrive::CommandAddr::Do_Step) {
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LOG_F(WARNING, "SWIM3: invalid command address on the phase lines!");
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return;
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}
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this->mode_reg |= SWIM3_GO_STEP;
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// step count > 1 requires periodic task
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if (this->step_count > 1) {
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this->step_timer_id = TimerManager::get_instance()->add_cyclic_timer(
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USECS_TO_NSECS(80),
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[this]() {
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this->do_step();
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}
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);
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}
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// perform the first step immediately
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do_step();
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}
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void Swim3Ctrl::stop_stepping()
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{
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// cancel stepping task
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if (this->step_timer_id) {
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TimerManager::get_instance()->cancel_timer(this->step_timer_id);
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}
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this->step_timer_id = 0;
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this->step_count = 0; // not sure this one is required
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}
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2022-02-13 02:07:32 +00:00
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void Swim3Ctrl::start_disk_access()
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2022-02-07 17:42:35 +00:00
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{
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2022-02-13 02:07:32 +00:00
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if (this->mode_reg & SWIM3_GO || this->access_timer_id) {
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LOG_F(ERROR, "SWIM3: another disk access is running!");
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return;
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}
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if (this->mode_reg & SWIM3_GO_STEP || this->step_timer_id) {
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LOG_F(ERROR, "SWIM3: disk access attempt while stepping is in progress!");
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return;
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}
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if (this->mode_reg & SWIM3_WR_MODE) {
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LOG_F(ERROR, "SWIM3: writing not implemented yet");
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return;
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}
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this->mode_reg |= SWIM3_GO;
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2022-02-15 14:55:16 +00:00
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LOG_F(9, "SWIM3: disk access started!");
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2022-02-13 02:07:32 +00:00
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2022-11-17 13:17:25 +00:00
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this->target_sect = this->first_sec;
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2022-02-15 14:55:16 +00:00
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2022-11-17 13:17:25 +00:00
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this->access_timer_id = TimerManager::get_instance()->add_oneshot_timer(
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this->int_drive->sync_to_disk(),
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[this]() {
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this->cur_state = SWIM3_ADDR_MARK_SEARCH;
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this->disk_access();
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}
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);
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}
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void Swim3Ctrl::disk_access()
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{
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MacSuperdrive::SectorHdr hdr;
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uint64_t delay;
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switch(this->cur_state) {
|
|
|
|
case SWIM3_ADDR_MARK_SEARCH:
|
|
|
|
hdr = this->int_drive->current_sector_header();
|
|
|
|
// update the corresponding SWIM3 registers
|
|
|
|
this->cur_track = ((hdr.side & 1) << 7) | (hdr.track & 0x7F);
|
|
|
|
this->cur_sector = 0x80 /* CRC/checksum valid */ | (hdr.sector & 0x7F);
|
|
|
|
this->format = hdr.format;
|
|
|
|
// generate ID_read interrupt
|
|
|
|
this->int_flags |= INT_ID_READ;
|
|
|
|
update_irq();
|
|
|
|
if ((this->cur_sector & 0x7F) == this->target_sect) {
|
|
|
|
// sector matches -> transfer its data
|
|
|
|
this->cur_state = SWIM3_DATA_XFER;
|
|
|
|
delay = this->int_drive->sector_data_delay();
|
|
|
|
} else {
|
|
|
|
// move to next address mark
|
|
|
|
this->cur_state = SWIM3_ADDR_MARK_SEARCH;
|
|
|
|
delay = this->int_drive->next_sector_delay();
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case SWIM3_DATA_XFER:
|
|
|
|
// transfer sector data over DMA
|
|
|
|
this->dma_ch->push_data(this->int_drive->get_sector_data_ptr(this->cur_sector & 0x7F), 512);
|
|
|
|
if (--this->xfer_cnt == 0) {
|
|
|
|
this->stop_disk_access();
|
|
|
|
// generate sector_done interrupt
|
|
|
|
this->int_flags |= INT_SECT_DONE;
|
|
|
|
update_irq();
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
this->cur_state = SWIM3_ADDR_MARK_SEARCH;
|
|
|
|
delay = this->int_drive->next_addr_mark_delay(&this->target_sect);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
LOG_F(ERROR, "SWIM3: unknown disk access phase 0x%X", this->cur_state);
|
|
|
|
return;
|
2022-02-13 02:07:32 +00:00
|
|
|
}
|
2022-11-17 13:17:25 +00:00
|
|
|
|
|
|
|
this->access_timer_id = TimerManager::get_instance()->add_oneshot_timer(
|
|
|
|
delay,
|
|
|
|
[this]() {
|
|
|
|
this->disk_access();
|
|
|
|
}
|
|
|
|
);
|
2022-02-07 17:42:35 +00:00
|
|
|
}
|
|
|
|
|
2022-02-13 02:07:32 +00:00
|
|
|
void Swim3Ctrl::stop_disk_access()
|
2022-02-07 17:42:35 +00:00
|
|
|
{
|
2022-02-13 02:07:32 +00:00
|
|
|
// cancel disk access timer
|
|
|
|
if (this->access_timer_id) {
|
|
|
|
TimerManager::get_instance()->cancel_timer(this->access_timer_id);
|
|
|
|
}
|
|
|
|
this->access_timer_id = 0;
|
2022-02-07 17:42:35 +00:00
|
|
|
}
|
2022-07-11 22:59:54 +00:00
|
|
|
|
2022-11-17 17:02:53 +00:00
|
|
|
void Swim3Ctrl::init_timer(const uint8_t start_val)
|
|
|
|
{
|
|
|
|
if (this->timer_val) {
|
|
|
|
LOG_F(WARNING, "SWIM3: attempt to re-arm the timer");
|
|
|
|
}
|
|
|
|
this->timer_val = start_val;
|
|
|
|
if (!this->timer_val) {
|
|
|
|
this->one_us_timer_start = 0;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
this->one_us_timer_start = TimerManager::get_instance()->current_time_ns();
|
|
|
|
|
|
|
|
this->one_us_timer_id = TimerManager::get_instance()->add_oneshot_timer(
|
|
|
|
this->timer_val * NS_PER_USEC,
|
|
|
|
[this]() {
|
|
|
|
this->timer_val = 0;
|
|
|
|
this->int_flags |= INT_TIMER_DONE;
|
|
|
|
update_irq();
|
|
|
|
}
|
|
|
|
);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint8_t Swim3Ctrl::calc_timer_val()
|
|
|
|
{
|
|
|
|
if (!this->timer_val) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t time_now = TimerManager::get_instance()->current_time_ns();
|
|
|
|
uint64_t us_elapsed = (time_now - this->one_us_timer_start) / NS_PER_USEC;
|
|
|
|
if (us_elapsed > this->timer_val) {
|
|
|
|
return 0;
|
|
|
|
} else {
|
|
|
|
return (this->timer_val - us_elapsed) & 0xFFU;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-09-03 22:20:29 +00:00
|
|
|
// floppy disk formats properties for the cases
|
|
|
|
// where disk format needs to be specified manually
|
|
|
|
static const std::vector<std::string> FloppyFormats = {
|
|
|
|
"", "GCR_400K", "GCR_800K", "MFM_720K", "MFM_1440K"
|
|
|
|
};
|
|
|
|
|
2022-07-11 22:59:54 +00:00
|
|
|
static const PropMap Swim3_Properties = {
|
|
|
|
{"fdd_img",
|
|
|
|
new StrProperty("")},
|
|
|
|
{"fdd_wr_prot",
|
2022-07-19 21:48:17 +00:00
|
|
|
new BinProperty(0)},
|
2022-09-03 22:20:29 +00:00
|
|
|
{"fdd_fmt",
|
|
|
|
new StrProperty("", FloppyFormats)},
|
2022-07-11 22:59:54 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static const DeviceDescription Swim3_Descriptor = {
|
|
|
|
Swim3Ctrl::create, {}, Swim3_Properties
|
|
|
|
};
|
|
|
|
|
|
|
|
REGISTER_DEVICE(Swim3, Swim3_Descriptor);
|