2020-02-28 16:04:28 +00:00
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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2023-12-01 19:38:29 +00:00
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Copyright (C) 2018-23 divingkatae and maximum
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2020-02-28 16:04:28 +00:00
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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2019-07-02 02:15:33 +00:00
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// The Power-specific opcodes for the processor - ppcopcodes.cpp
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// Any shared opcodes are in ppcopcodes.cpp
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2019-12-27 19:10:36 +00:00
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#include "ppcemu.h"
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2024-03-22 15:01:29 +00:00
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#include "ppcmacros.h"
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2019-12-27 19:00:53 +00:00
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#include "ppcmmu.h"
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2023-11-03 07:21:33 +00:00
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#include <stdint.h>
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2019-07-02 02:15:33 +00:00
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2020-10-17 21:30:37 +00:00
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// Affects the XER register's SO and OV Bits
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2019-07-02 02:15:33 +00:00
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2020-10-17 21:30:37 +00:00
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inline void power_setsoov(uint32_t a, uint32_t b, uint32_t d) {
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if ((a ^ b) & (a ^ d) & 0x80000000UL) {
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ppc_state.spr[SPR::XER] |= 0xC0000000UL;
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2020-05-12 18:55:45 +00:00
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} else {
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2020-10-17 21:30:37 +00:00
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ppc_state.spr[SPR::XER] &= 0xBFFFFFFFUL;
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2019-07-02 02:15:33 +00:00
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}
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}
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2021-10-23 19:00:31 +00:00
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/** mask generator for rotate and shift instructions (§ 4.2.1.4 PowerpC PEM) */
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2021-10-02 05:37:28 +00:00
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static inline uint32_t power_rot_mask(unsigned rot_mb, unsigned rot_me) {
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uint32_t m1 = 0xFFFFFFFFUL >> rot_mb;
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2024-02-23 02:46:34 +00:00
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uint32_t m2 = uint32_t(0xFFFFFFFFUL << (31 - rot_me));
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2021-10-02 05:37:28 +00:00
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return ((rot_mb <= rot_me) ? m2 & m1 : m1 | m2);
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}
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2024-03-24 19:21:19 +00:00
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template <bool rec, bool ov>
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2020-10-18 04:46:38 +00:00
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void dppc_interpreter::power_abs() {
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2024-03-22 15:01:29 +00:00
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uint32_t ppc_result_d;
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ppc_grab_regsda(ppc_cur_instruction);
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2020-01-26 02:30:55 +00:00
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if (ppc_result_a == 0x80000000) {
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2019-07-02 02:15:33 +00:00
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ppc_result_d = ppc_result_a;
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2024-03-24 19:21:19 +00:00
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if (ov)
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2021-10-02 05:37:28 +00:00
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ppc_state.spr[SPR::XER] |= 0xC0000000;
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2019-07-02 02:15:33 +00:00
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2020-05-12 18:55:45 +00:00
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} else {
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2019-07-02 02:15:33 +00:00
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ppc_result_d = ppc_result_a & 0x7FFFFFFF;
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}
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2024-03-24 19:21:19 +00:00
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if (rec)
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2020-10-17 21:30:37 +00:00
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ppc_changecrf0(ppc_result_d);
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2019-07-02 02:15:33 +00:00
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2024-03-22 15:01:29 +00:00
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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2019-07-02 02:15:33 +00:00
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}
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2024-03-24 19:21:19 +00:00
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template void dppc_interpreter::power_abs<RC0, OV0>();
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template void dppc_interpreter::power_abs<RC0, OV1>();
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template void dppc_interpreter::power_abs<RC1, OV0>();
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template void dppc_interpreter::power_abs<RC1, OV1>();
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2020-10-18 04:46:38 +00:00
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void dppc_interpreter::power_clcs() {
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2024-03-22 15:01:29 +00:00
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uint32_t ppc_result_d;
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ppc_grab_regsda(ppc_cur_instruction);
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2020-01-26 02:30:55 +00:00
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switch (reg_a) {
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2021-10-02 05:37:28 +00:00
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case 12: //instruction cache line size
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case 13: //data cache line size
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case 14: //minimum line size
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case 15: //maximum line size
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ppc_result_d = 64;
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2020-01-26 02:30:55 +00:00
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break;
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default:
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ppc_result_d = 0;
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2019-07-02 02:15:33 +00:00
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}
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2024-03-22 15:01:29 +00:00
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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2019-07-02 02:15:33 +00:00
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}
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2024-03-24 19:21:19 +00:00
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template <bool rec, bool ov>
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2020-10-18 04:46:38 +00:00
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void dppc_interpreter::power_div() {
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2024-03-22 15:01:29 +00:00
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uint32_t ppc_result_d;
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ppc_grab_regsdab(ppc_cur_instruction);
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2023-12-01 19:38:29 +00:00
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2024-02-24 21:51:05 +00:00
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uint64_t dividend = ((uint64_t)ppc_result_a << 32) | ppc_state.spr[SPR::MQ];
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2023-12-03 10:05:18 +00:00
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int32_t divisor = ppc_result_b;
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2023-12-01 19:38:29 +00:00
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if ((ppc_result_a == 0x80000000UL && divisor == -1) || !divisor) {
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ppc_state.spr[SPR::MQ] = 0;
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2024-03-22 15:01:29 +00:00
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ppc_result_d = 0x80000000UL; // -2^31 aka INT32_MIN
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2023-12-01 19:38:29 +00:00
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} else {
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2024-03-22 15:01:29 +00:00
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ppc_result_d = uint32_t(dividend / divisor);
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2023-12-01 19:38:29 +00:00
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ppc_state.spr[SPR::MQ] = dividend % divisor;
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}
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2019-07-02 02:15:33 +00:00
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2024-03-24 19:21:19 +00:00
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if (ov)
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2020-10-17 21:30:37 +00:00
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power_setsoov(ppc_result_b, ppc_result_a, ppc_result_d);
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2024-03-24 19:21:19 +00:00
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if (rec)
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2020-10-17 21:30:37 +00:00
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ppc_changecrf0(ppc_result_d);
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2019-07-02 02:15:33 +00:00
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2024-03-22 15:01:29 +00:00
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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2019-07-02 02:15:33 +00:00
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}
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2024-03-24 19:21:19 +00:00
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template void dppc_interpreter::power_div<RC0, OV0>();
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template void dppc_interpreter::power_div<RC0, OV1>();
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template void dppc_interpreter::power_div<RC1, OV0>();
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template void dppc_interpreter::power_div<RC1, OV1>();
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template <bool rec, bool ov>
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2020-10-18 04:46:38 +00:00
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void dppc_interpreter::power_divs() {
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2024-03-22 15:01:29 +00:00
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ppc_grab_regsdab(ppc_cur_instruction);
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uint32_t ppc_result_d = ppc_result_a / ppc_result_b;
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2020-03-05 04:29:04 +00:00
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ppc_state.spr[SPR::MQ] = (ppc_result_a % ppc_result_b);
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2019-07-02 02:15:33 +00:00
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2024-03-24 19:21:19 +00:00
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if (ov)
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2020-10-17 21:30:37 +00:00
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power_setsoov(ppc_result_b, ppc_result_a, ppc_result_d);
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2024-03-24 19:21:19 +00:00
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if (rec)
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2020-10-17 21:30:37 +00:00
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ppc_changecrf0(ppc_result_d);
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2019-07-02 02:15:33 +00:00
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2024-03-22 15:01:29 +00:00
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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2019-07-02 02:15:33 +00:00
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}
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2024-03-24 19:21:19 +00:00
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template void dppc_interpreter::power_divs<RC0, OV0>();
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template void dppc_interpreter::power_divs<RC0, OV1>();
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template void dppc_interpreter::power_divs<RC1, OV0>();
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template void dppc_interpreter::power_divs<RC1, OV1>();
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template <bool rec, bool ov>
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2020-10-18 04:46:38 +00:00
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void dppc_interpreter::power_doz() {
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2024-03-22 15:01:29 +00:00
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ppc_grab_regsdab(ppc_cur_instruction);
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uint32_t ppc_result_d = (int32_t(ppc_result_a) >= int32_t(ppc_result_b))\
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? 0 : ppc_result_b - ppc_result_a;
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2019-07-02 02:15:33 +00:00
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2024-03-24 19:21:19 +00:00
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if (rec)
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2020-10-17 21:30:37 +00:00
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ppc_changecrf0(ppc_result_d);
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2024-03-24 19:21:19 +00:00
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if (ov)
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2021-10-02 05:37:28 +00:00
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power_setsoov(ppc_result_a, ppc_result_b, ppc_result_d);
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2019-07-02 02:15:33 +00:00
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2024-03-22 15:01:29 +00:00
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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2019-07-02 02:15:33 +00:00
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}
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2024-03-24 19:21:19 +00:00
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template void dppc_interpreter::power_doz<RC0, OV0>();
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template void dppc_interpreter::power_doz<RC0, OV1>();
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template void dppc_interpreter::power_doz<RC1, OV0>();
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template void dppc_interpreter::power_doz<RC1, OV1>();
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2020-10-18 04:46:38 +00:00
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void dppc_interpreter::power_dozi() {
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2024-03-22 15:01:29 +00:00
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uint32_t ppc_result_d;
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ppc_grab_regsdasimm(ppc_cur_instruction);
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2020-01-26 02:30:55 +00:00
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if (((int32_t)ppc_result_a) > simm) {
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2019-07-02 02:15:33 +00:00
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ppc_result_d = 0;
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2020-05-12 18:55:45 +00:00
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} else {
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2021-10-02 05:37:28 +00:00
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ppc_result_d = simm - ppc_result_a;
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2019-07-02 02:15:33 +00:00
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}
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2024-03-22 15:01:29 +00:00
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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2019-07-02 02:15:33 +00:00
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}
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2024-03-24 19:21:19 +00:00
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template <bool rec>
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2020-10-18 04:46:38 +00:00
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void dppc_interpreter::power_lscbx() {
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2024-03-22 15:01:29 +00:00
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ppc_grab_regsdab(ppc_cur_instruction);
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2024-02-25 03:44:46 +00:00
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ppc_effective_address = ppc_result_b + (reg_a ? ppc_result_a : 0);
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2021-10-02 05:37:28 +00:00
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2024-02-24 21:44:45 +00:00
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uint8_t return_value = 0;
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uint32_t bytes_to_load = (ppc_state.spr[SPR::XER] & 0x7F);
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2021-10-02 05:37:28 +00:00
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uint32_t bytes_copied = 0;
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2024-02-24 21:44:45 +00:00
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uint8_t matching_byte = (uint8_t)(ppc_state.spr[SPR::XER] >> 8);
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2024-03-22 15:01:29 +00:00
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uint32_t ppc_result_d = 0;
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2021-10-02 05:37:28 +00:00
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2022-11-13 03:17:04 +00:00
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// for storing each byte
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2024-02-24 21:44:45 +00:00
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uint32_t bitmask = 0xFF000000;
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uint8_t shift_amount = 24;
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2021-10-02 05:37:28 +00:00
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while (bytes_to_load > 0) {
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return_value = mmu_read_vmem<uint8_t>(ppc_effective_address);
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2024-02-24 21:44:45 +00:00
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ppc_result_d = (ppc_result_d & ~bitmask) | (return_value << shift_amount);
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if (!shift_amount) {
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if (reg_d != reg_a && reg_d != reg_b)
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2024-03-22 15:01:29 +00:00
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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2022-11-15 14:40:37 +00:00
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reg_d = (reg_d + 1) & 31;
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bitmask = 0xFF000000;
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shift_amount = 24;
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2024-02-24 21:44:45 +00:00
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} else {
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2022-11-15 14:40:37 +00:00
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bitmask >>= 8;
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shift_amount -= 8;
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2019-07-02 02:15:33 +00:00
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}
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2021-10-02 05:37:28 +00:00
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ppc_effective_address++;
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2022-11-15 14:40:37 +00:00
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bytes_copied++;
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2021-10-02 05:37:28 +00:00
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bytes_to_load--;
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2022-11-15 15:01:57 +00:00
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if (return_value == matching_byte)
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break;
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2021-10-02 05:37:28 +00:00
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}
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2024-02-24 21:44:45 +00:00
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// store partiallly loaded register if any
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if (shift_amount != 24 && reg_d != reg_a && reg_d != reg_b)
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2024-03-22 15:01:29 +00:00
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ppc_store_iresult_reg(reg_d, ppc_result_d);
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2019-07-02 02:15:33 +00:00
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2024-02-24 21:44:45 +00:00
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ppc_state.spr[SPR::XER] = (ppc_state.spr[SPR::XER] & ~0x7F) | bytes_copied;
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2020-10-17 21:30:37 +00:00
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2024-03-24 19:21:19 +00:00
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if (rec)
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2020-10-17 21:30:37 +00:00
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ppc_changecrf0(ppc_result_d);
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2019-07-02 02:15:33 +00:00
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}
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2024-03-24 19:21:19 +00:00
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template void dppc_interpreter::power_lscbx<RC0>();
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template void dppc_interpreter::power_lscbx<RC1>();
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template <bool rec>
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2020-10-18 04:46:38 +00:00
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void dppc_interpreter::power_maskg() {
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2024-03-22 15:01:29 +00:00
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ppc_grab_regssab(ppc_cur_instruction);
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2020-05-12 18:55:45 +00:00
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uint32_t mask_start = ppc_result_d & 31;
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uint32_t mask_end = ppc_result_b & 31;
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2019-07-02 02:15:33 +00:00
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uint32_t insert_mask = 0;
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2020-01-26 02:30:55 +00:00
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if (mask_start < (mask_end + 1)) {
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2021-10-02 05:37:28 +00:00
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insert_mask = power_rot_mask(mask_start, mask_end);
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2021-10-23 19:00:31 +00:00
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}
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2021-10-02 05:37:28 +00:00
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else if (mask_start == (mask_end + 1)) {
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2019-07-02 02:15:33 +00:00
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insert_mask = 0xFFFFFFFF;
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2021-10-23 19:00:31 +00:00
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}
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2021-10-02 05:37:28 +00:00
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else {
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insert_mask = ~(power_rot_mask(mask_end + 1, mask_start - 1));
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2019-07-02 02:15:33 +00:00
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}
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ppc_result_a = insert_mask;
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2024-03-24 19:21:19 +00:00
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if (rec)
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2020-10-17 21:30:37 +00:00
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ppc_changecrf0(ppc_result_d);
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2019-07-02 02:15:33 +00:00
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2024-03-22 15:01:29 +00:00
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ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_maskg<RC0>();
|
|
|
|
template void dppc_interpreter::power_maskg<true>();
|
|
|
|
|
|
|
|
template <bool rec>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_maskir() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regssab(ppc_cur_instruction);
|
2023-12-01 19:38:29 +00:00
|
|
|
ppc_result_a = (ppc_result_a & ~ppc_result_b) | (ppc_result_d & ppc_result_b);
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2020-10-17 21:30:37 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_maskir<RC0>();
|
|
|
|
template void dppc_interpreter::power_maskir<true>();
|
|
|
|
|
|
|
|
template <bool rec, bool ov>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_mul() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regsdab(ppc_cur_instruction);
|
2019-07-02 02:15:33 +00:00
|
|
|
uint64_t product;
|
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
product = ((uint64_t)ppc_result_a) * ((uint64_t)ppc_result_b);
|
2024-03-22 15:01:29 +00:00
|
|
|
uint32_t ppc_result_d = ((uint32_t)(product >> 32));
|
2020-03-05 04:29:04 +00:00
|
|
|
ppc_state.spr[SPR::MQ] = ((uint32_t)(product));
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2020-10-17 21:30:37 +00:00
|
|
|
ppc_changecrf0(ppc_result_d);
|
2024-03-24 19:21:19 +00:00
|
|
|
if (ov)
|
|
|
|
power_setsoov(ppc_result_a, ppc_result_b, ppc_result_d);
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_d, ppc_result_d);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_mul<RC0, OV0>();
|
|
|
|
template void dppc_interpreter::power_mul<RC0, OV1>();
|
|
|
|
template void dppc_interpreter::power_mul<RC1, OV0>();
|
|
|
|
template void dppc_interpreter::power_mul<RC1, OV1>();
|
|
|
|
|
|
|
|
template <bool rec, bool ov>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_nabs() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regsda(ppc_cur_instruction);
|
|
|
|
uint32_t ppc_result_d = ppc_result_a & 0x80000000 ? ppc_result_a : -ppc_result_a;
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2020-10-17 21:30:37 +00:00
|
|
|
ppc_changecrf0(ppc_result_d);
|
2024-03-24 19:21:19 +00:00
|
|
|
if (ov)
|
|
|
|
ppc_state.spr[SPR::XER] &= 0xBFFFFFFFUL;
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_d, ppc_result_d);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_nabs<RC0, OV0>();
|
|
|
|
template void dppc_interpreter::power_nabs<RC0, OV1>();
|
|
|
|
template void dppc_interpreter::power_nabs<RC1, OV0>();
|
|
|
|
template void dppc_interpreter::power_nabs<RC1, OV1>();
|
|
|
|
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_rlmi() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regssab(ppc_cur_instruction);
|
2020-05-12 18:55:45 +00:00
|
|
|
unsigned rot_mb = (ppc_cur_instruction >> 6) & 31;
|
|
|
|
unsigned rot_me = (ppc_cur_instruction >> 1) & 31;
|
2021-10-02 05:37:28 +00:00
|
|
|
unsigned rot_sh = ppc_result_b & 31;
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2021-10-02 05:37:28 +00:00
|
|
|
uint32_t r = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
|
|
|
|
uint32_t mask = power_rot_mask(rot_mb, rot_me);
|
|
|
|
|
|
|
|
ppc_result_a = ((r & mask) | (ppc_result_a & ~mask));
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if ((ppc_cur_instruction & 0x01) == 1)
|
2021-10-02 05:37:28 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template <bool rec>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_rrib() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regssab(ppc_cur_instruction);
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2020-01-26 02:30:55 +00:00
|
|
|
if (ppc_result_d & 0x80000000) {
|
2021-10-02 05:37:28 +00:00
|
|
|
ppc_result_a |= ((ppc_result_d & 0x80000000) >> ppc_result_b);
|
2020-05-12 18:55:45 +00:00
|
|
|
} else {
|
2021-10-02 05:37:28 +00:00
|
|
|
ppc_result_a &= ~((ppc_result_d & 0x80000000) >> ppc_result_b);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
2020-10-17 21:30:37 +00:00
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2020-10-17 21:30:37 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_rrib<RC0>();
|
|
|
|
template void dppc_interpreter::power_rrib<RC1>();
|
|
|
|
|
|
|
|
template <bool rec>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_sle() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regssab(ppc_cur_instruction);
|
2021-10-02 05:37:28 +00:00
|
|
|
unsigned rot_sh = ppc_result_b & 31;
|
|
|
|
|
|
|
|
ppc_result_a = ppc_result_d << rot_sh;
|
|
|
|
ppc_state.spr[SPR::MQ] = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
|
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2020-10-17 21:30:37 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_sle<RC0>();
|
|
|
|
template void dppc_interpreter::power_sle<RC1>();
|
|
|
|
|
|
|
|
template <bool rec>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_sleq() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regssab(ppc_cur_instruction);
|
2021-10-02 05:37:28 +00:00
|
|
|
unsigned rot_sh = ppc_result_b & 31;
|
|
|
|
uint32_t r = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
|
|
|
|
uint32_t mask = power_rot_mask(0, 31 - rot_sh);
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2021-10-02 05:37:28 +00:00
|
|
|
ppc_result_a = ((r & mask) | (ppc_state.spr[SPR::MQ] & ~mask));
|
|
|
|
ppc_state.spr[SPR::MQ] = r;
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2020-10-17 21:30:37 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_sleq<RC0>();
|
|
|
|
template void dppc_interpreter::power_sleq<RC1>();
|
|
|
|
|
|
|
|
template <bool rec>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_sliq() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regssa(ppc_cur_instruction);
|
2020-05-12 18:55:45 +00:00
|
|
|
unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2021-10-02 05:37:28 +00:00
|
|
|
ppc_result_a = ppc_result_d << rot_sh;
|
|
|
|
ppc_state.spr[SPR::MQ] = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2020-10-17 21:30:37 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_sliq<RC0>();
|
|
|
|
template void dppc_interpreter::power_sliq<RC1>();
|
|
|
|
|
|
|
|
template <bool rec>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_slliq() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regssa(ppc_cur_instruction);
|
2020-05-12 18:55:45 +00:00
|
|
|
unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
|
2021-10-02 05:37:28 +00:00
|
|
|
uint32_t r = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
|
|
|
|
uint32_t mask = power_rot_mask(0, 31 - rot_sh);
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2021-10-02 05:37:28 +00:00
|
|
|
ppc_result_a = ((r & mask) | (ppc_state.spr[SPR::MQ] & ~mask));
|
|
|
|
ppc_state.spr[SPR::MQ] = r;
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2020-10-17 21:30:37 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_slliq<RC0>();
|
|
|
|
template void dppc_interpreter::power_slliq<RC1>();
|
|
|
|
|
|
|
|
template <bool rec>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_sllq() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regssab(ppc_cur_instruction);
|
2021-10-02 05:37:28 +00:00
|
|
|
unsigned rot_sh = ppc_result_b & 31;
|
|
|
|
uint32_t r = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
|
|
|
|
uint32_t mask = power_rot_mask(0, 31 - rot_sh);
|
|
|
|
|
|
|
|
if (ppc_result_b >= 0x20) {
|
|
|
|
ppc_result_a = (ppc_state.spr[SPR::MQ] & mask);
|
2021-10-23 19:00:31 +00:00
|
|
|
}
|
2021-10-02 05:37:28 +00:00
|
|
|
else {
|
|
|
|
ppc_result_a = ((r & mask) | (ppc_state.spr[SPR::MQ] & ~mask));
|
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2021-10-02 05:37:28 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_sllq<RC0>();
|
|
|
|
template void dppc_interpreter::power_sllq<RC1>();
|
|
|
|
|
|
|
|
template <bool rec>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_slq() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regssab(ppc_cur_instruction);
|
2021-10-02 05:37:28 +00:00
|
|
|
unsigned rot_sh = ppc_result_b & 31;
|
|
|
|
|
|
|
|
if (ppc_result_b >= 0x20) {
|
|
|
|
ppc_result_a = ppc_result_d << rot_sh;
|
|
|
|
} else {
|
|
|
|
ppc_result_a = 0;
|
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2021-10-02 05:37:28 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
|
|
|
|
|
|
|
ppc_state.spr[SPR::MQ] = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_slq<RC0>();
|
|
|
|
template void dppc_interpreter::power_slq<RC1>();
|
|
|
|
|
|
|
|
template <bool rec>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_sraiq() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regssa(ppc_cur_instruction);
|
2021-10-02 05:37:28 +00:00
|
|
|
unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
|
|
|
|
uint32_t mask = (1 << rot_sh) - 1;
|
|
|
|
ppc_result_a = (int32_t)ppc_result_d >> rot_sh;
|
2024-02-21 01:15:08 +00:00
|
|
|
ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
|
2021-10-02 05:37:28 +00:00
|
|
|
|
|
|
|
if ((ppc_result_d & 0x80000000UL) && (ppc_result_d & mask)) {
|
|
|
|
ppc_state.spr[SPR::XER] |= 0x20000000UL;
|
|
|
|
} else {
|
|
|
|
ppc_state.spr[SPR::XER] &= 0xDFFFFFFFUL;
|
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2021-10-02 05:37:28 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_sraiq<RC0>();
|
|
|
|
template void dppc_interpreter::power_sraiq<RC1>();
|
|
|
|
|
|
|
|
template <bool rec>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_sraq() {
|
2024-03-22 15:01:29 +00:00
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ppc_grab_regssab(ppc_cur_instruction);
|
2021-10-02 05:37:28 +00:00
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unsigned rot_sh = ppc_result_b & 0x1F;
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uint32_t mask = (1 << rot_sh) - 1;
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ppc_result_a = (int32_t)ppc_result_d >> rot_sh;
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ppc_state.spr[SPR::MQ] = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
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if ((ppc_result_d & 0x80000000UL) && (ppc_result_d & mask)) {
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ppc_state.spr[SPR::XER] |= 0x20000000UL;
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|
} else {
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|
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ppc_state.spr[SPR::XER] &= 0xDFFFFFFFUL;
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|
}
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|
2024-02-21 01:15:08 +00:00
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|
ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
|
2021-10-02 05:37:28 +00:00
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|
|
2024-03-24 19:21:19 +00:00
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|
if (rec)
|
2021-10-02 05:37:28 +00:00
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ppc_changecrf0(ppc_result_a);
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2024-03-22 15:01:29 +00:00
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ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
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}
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2024-03-24 19:21:19 +00:00
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template void dppc_interpreter::power_sraq<RC0>();
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template void dppc_interpreter::power_sraq<RC1>();
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template <bool rec>
|
2020-10-18 04:46:38 +00:00
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void dppc_interpreter::power_sre() {
|
2024-03-22 15:01:29 +00:00
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ppc_grab_regssab(ppc_cur_instruction);
|
2021-10-02 05:37:28 +00:00
|
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unsigned rot_sh = ppc_result_b & 31;
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ppc_result_a = ppc_result_d >> rot_sh;
|
2024-02-21 01:15:08 +00:00
|
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|
ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
|
2021-10-02 05:37:28 +00:00
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|
|
2024-03-24 19:21:19 +00:00
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|
|
if (rec)
|
2020-10-17 21:30:37 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
2021-10-02 05:37:28 +00:00
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|
2024-03-22 15:01:29 +00:00
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|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
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|
}
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|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_sre<RC0>();
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template void dppc_interpreter::power_sre<RC1>();
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template <bool rec>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_srea() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regssab(ppc_cur_instruction);
|
2021-10-02 05:37:28 +00:00
|
|
|
unsigned rot_sh = ppc_result_b & 0x1F;
|
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|
|
ppc_result_a = (int32_t)ppc_result_d >> rot_sh;
|
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|
ppc_state.spr[SPR::MQ] = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
|
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|
|
if ((ppc_result_d & 0x80000000UL) && (ppc_result_d & rot_sh)) {
|
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|
|
ppc_state.spr[SPR::XER] |= 0x20000000UL;
|
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|
} else {
|
|
|
|
ppc_state.spr[SPR::XER] &= 0xDFFFFFFFUL;
|
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2021-10-02 05:37:28 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_srea<RC0>();
|
|
|
|
template void dppc_interpreter::power_srea<RC1>();
|
|
|
|
|
|
|
|
template <bool rec>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_sreq() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regssab(ppc_cur_instruction);
|
2020-05-12 18:55:45 +00:00
|
|
|
unsigned rot_sh = ppc_result_b & 31;
|
2021-10-02 05:37:28 +00:00
|
|
|
unsigned mask = power_rot_mask(rot_sh, 31);
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2021-10-02 05:37:28 +00:00
|
|
|
ppc_result_a = ((rot_sh & mask) | (ppc_state.spr[SPR::MQ] & ~mask));
|
|
|
|
ppc_state.spr[SPR::MQ] = rot_sh;
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2020-10-17 21:30:37 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_sreq<RC0>();
|
|
|
|
template void dppc_interpreter::power_sreq<RC1>();
|
|
|
|
|
|
|
|
template <bool rec>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_sriq() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regssa(ppc_cur_instruction);
|
2021-10-02 05:37:28 +00:00
|
|
|
unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
|
|
|
|
ppc_result_a = ppc_result_d >> rot_sh;
|
2024-02-18 11:47:21 +00:00
|
|
|
ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2020-10-17 21:30:37 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_sriq<RC0>();
|
|
|
|
template void dppc_interpreter::power_sriq<RC1>();
|
|
|
|
|
|
|
|
template <bool rec>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_srliq() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regssa(ppc_cur_instruction);
|
2021-10-02 05:37:28 +00:00
|
|
|
unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
|
|
|
|
|
2024-02-21 01:15:08 +00:00
|
|
|
uint32_t r = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
|
2021-10-02 05:37:28 +00:00
|
|
|
unsigned mask = power_rot_mask(rot_sh, 31);
|
|
|
|
|
|
|
|
ppc_result_a = ((r & mask) | (ppc_state.spr[SPR::MQ] & ~mask));
|
|
|
|
ppc_state.spr[SPR::MQ] = r;
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2021-10-02 05:37:28 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_srliq<RC0>();
|
|
|
|
template void dppc_interpreter::power_srliq<RC1>();
|
|
|
|
|
|
|
|
template <bool rec>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_srlq() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regssab(ppc_cur_instruction);
|
2021-10-02 05:37:28 +00:00
|
|
|
unsigned rot_sh = ppc_result_b & 31;
|
2024-02-21 01:15:08 +00:00
|
|
|
uint32_t r = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
|
2021-10-02 05:37:28 +00:00
|
|
|
unsigned mask = power_rot_mask(rot_sh, 31);
|
|
|
|
|
|
|
|
if (ppc_result_b >= 0x20) {
|
|
|
|
ppc_result_a = (ppc_state.spr[SPR::MQ] & mask);
|
2021-10-23 19:00:31 +00:00
|
|
|
}
|
2021-10-02 05:37:28 +00:00
|
|
|
else {
|
|
|
|
ppc_result_a = ((r & mask) | (ppc_state.spr[SPR::MQ] & ~mask));
|
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2021-10-02 05:37:28 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2019-07-02 02:15:33 +00:00
|
|
|
}
|
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
template void dppc_interpreter::power_srlq<RC0>();
|
|
|
|
template void dppc_interpreter::power_srlq<RC1>();
|
|
|
|
|
|
|
|
template <bool rec>
|
2020-10-18 04:46:38 +00:00
|
|
|
void dppc_interpreter::power_srq() {
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_grab_regssab(ppc_cur_instruction);
|
2021-10-02 05:37:28 +00:00
|
|
|
unsigned rot_sh = ppc_result_b & 31;
|
|
|
|
|
|
|
|
if (ppc_result_b >= 0x20) {
|
|
|
|
ppc_result_a = 0;
|
|
|
|
} else {
|
|
|
|
ppc_result_a = ppc_result_d >> rot_sh;
|
|
|
|
}
|
|
|
|
|
2024-02-21 01:15:08 +00:00
|
|
|
ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
|
2021-10-02 05:37:28 +00:00
|
|
|
|
2024-03-24 19:21:19 +00:00
|
|
|
if (rec)
|
2021-10-02 05:37:28 +00:00
|
|
|
ppc_changecrf0(ppc_result_a);
|
|
|
|
|
2024-03-22 15:01:29 +00:00
|
|
|
ppc_store_iresult_reg(reg_a, ppc_result_a);
|
2021-08-03 14:01:32 +00:00
|
|
|
}
|
2024-03-24 19:21:19 +00:00
|
|
|
|
|
|
|
template void dppc_interpreter::power_srq<RC0>();
|
|
|
|
template void dppc_interpreter::power_srq<RC1>();
|