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atimach64gx: Add io_access_allowed.
This method is used by both pci_io_read and pci_io_write to determine if ISA type I/O access is allowed. The SPARSE_IO_BASE I/O address is defined. This I/O range is not defined by an I/O BAR.
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@ -248,32 +248,45 @@ static const uint32_t io_idx_to_reg_offset[32] = {
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ATI_CRTC_H_TOTAL_DISP,
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};
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enum {
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SPARSE_IO_BASE = 0x2EC
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};
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bool AtiMach64Gx::io_access_allowed(uint32_t offset) {
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if ((offset & 0xFFFF03FC) == SPARSE_IO_BASE) {
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if (this->command & 1) {
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return true;
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}
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LOG_F(WARNING, "ATI I/O space disabled in the command reg");
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}
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return false;
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}
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bool AtiMach64Gx::pci_io_read(uint32_t offset, uint32_t size, uint32_t* res)
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{
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*res = 0;
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// check for valid I/O base and I/O access permission
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if ((offset & 0x3FC) != 0x2EC || !(this->command & 1)) {
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if (!this->io_access_allowed(offset)) {
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return false;
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}
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uint32_t result = 0;
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// convert ISA-style I/O address to MMIO register offset
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offset = io_idx_to_reg_offset[(offset >> 10) & 0x1F] * 4 + (offset & 3);
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// CONFIG_CNTL is accessible from I/O space only
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if ((offset >> 2) == ATI_CONFIG_CNTL) {
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*res = read_mem(((uint8_t *)&this->config_cntl) + (offset & 3), size);
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result = read_mem(((uint8_t *)&this->config_cntl) + (offset & 3), size);
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} else {
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*res = BYTESWAP_SIZED(this->read_reg(offset, size), size);
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result = BYTESWAP_SIZED(this->read_reg(offset, size), size);
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}
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*res = result;
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return true;
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}
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bool AtiMach64Gx::pci_io_write(uint32_t offset, uint32_t value, uint32_t size)
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{
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// check for valid I/O base and I/O access permission
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if ((offset & 0x3FC) != 0x2EC || !(this->command & 1)) {
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if (!this->io_access_allowed(offset)) {
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return false;
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}
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@ -57,6 +57,7 @@ protected:
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void notify_bar_change(int bar_num);
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const char* get_reg_name(uint32_t reg_offset);
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const char* rgb514_get_reg_name(uint32_t reg_offset);
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bool io_access_allowed(uint32_t offset);
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uint32_t read_reg(uint32_t reg_offset, uint32_t size);
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void write_reg(uint32_t reg_offset, uint32_t value, uint32_t size);
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void enable_crtc_internal();
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