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Tweaking conditional branch instructions
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d279ada718
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@ -1142,7 +1142,7 @@ void dppc_interpreter::ppc_bc() {
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}
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if (l)
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ppc_state.spr[SPR::LR] = ppc_state.pc + 4;
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ppc_state.spr[SPR::LR] = uint32_t(ppc_state.pc + 4);
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}
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template void dppc_interpreter::ppc_bc<LK0, AA0>();
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@ -1159,16 +1159,17 @@ void dppc_interpreter::ppc_bcctr() {
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uint32_t ctr = ppc_state.spr[SPR::CTR];
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uint32_t new_ctr;
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if (for601) {
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new_ctr = ctr - 1;
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if (!(br_bo & 0x04)) {
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ppc_state.spr[SPR::CTR] = new_ctr; /* decrement CTR */
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}
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}
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else {
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if (!(br_bo & 0x04))
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ppc_state.spr[SPR::CTR] = new_ctr;
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ctr_ok = (br_bo & 0x04) | ((new_ctr != 0) == !(br_bo & 0x02));
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} else {
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new_ctr = ctr;
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ctr_ok = 1;
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}
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ctr_ok = (br_bo & 0x04) | ((new_ctr != 0) == !(br_bo & 0x02));
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cnd_ok = (br_bo & 0x10) | (!(ppc_state.cr & (0x80000000UL >> br_bi)) == !(br_bo & 0x08));
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if (ctr_ok && cnd_ok) {
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@ -1177,7 +1178,7 @@ void dppc_interpreter::ppc_bcctr() {
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}
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if (l)
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ppc_state.spr[SPR::LR] = ppc_state.pc + 4;
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ppc_state.spr[SPR::LR] = uint32_t(ppc_state.pc + 4);
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}
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template void dppc_interpreter::ppc_bcctr<LK0, NOT601>();
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@ -1204,7 +1205,7 @@ void dppc_interpreter::ppc_bclr() {
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}
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if (l)
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ppc_state.spr[SPR::LR] = ppc_state.pc + 4;
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ppc_state.spr[SPR::LR] = uint32_t(ppc_state.pc + 4);
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}
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template void dppc_interpreter::ppc_bclr<LK0>();
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