mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-12-24 12:30:05 +00:00
mesh: fix writes to BusStatus0 & BusStatus1 registers.
This commit is contained in:
parent
ebc618adea
commit
19ecc4f945
@ -115,19 +115,11 @@ void MeshController::write(uint8_t reg_offset, uint8_t value) {
|
|||||||
case MeshReg::Sequence:
|
case MeshReg::Sequence:
|
||||||
perform_command(value);
|
perform_command(value);
|
||||||
break;
|
break;
|
||||||
|
case MeshReg::BusStatus0:
|
||||||
|
this->update_bus_status((this->bus_stat & 0xFF00U) | value);
|
||||||
|
break;
|
||||||
case MeshReg::BusStatus1:
|
case MeshReg::BusStatus1:
|
||||||
new_stat = value << 8;
|
this->update_bus_status((this->bus_stat & 0xFFU) | (value << 8));
|
||||||
if (new_stat != this->bus_stat) {
|
|
||||||
for (uint16_t mask = SCSI_CTRL_RST; mask >= SCSI_CTRL_SEL; mask >>= 1) {
|
|
||||||
if ((new_stat ^ this->bus_stat) & mask) {
|
|
||||||
if (new_stat & mask)
|
|
||||||
this->bus_obj->assert_ctrl_line(this->src_id, mask);
|
|
||||||
else
|
|
||||||
this->bus_obj->release_ctrl_line(this->src_id, mask);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
this->bus_stat = new_stat;
|
|
||||||
}
|
|
||||||
break;
|
break;
|
||||||
case MeshReg::IntMask:
|
case MeshReg::IntMask:
|
||||||
this->int_mask = value;
|
this->int_mask = value;
|
||||||
@ -248,6 +240,36 @@ void MeshController::perform_command(const uint8_t cmd) {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void MeshController::update_bus_status(const uint16_t new_stat) {
|
||||||
|
uint16_t mask;
|
||||||
|
|
||||||
|
// update the lower part (BusStatus0)
|
||||||
|
if ((new_stat ^ this->bus_stat) & 0xFF) {
|
||||||
|
for (mask = SCSI_CTRL_REQ; mask >= SCSI_CTRL_IO; mask >>= 1) {
|
||||||
|
if ((new_stat ^ this->bus_stat) & mask) {
|
||||||
|
if (new_stat & mask)
|
||||||
|
this->bus_obj->assert_ctrl_line(this->src_id, mask);
|
||||||
|
else
|
||||||
|
this->bus_obj->release_ctrl_line(this->src_id, mask);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// update the upper part (BusStatus1)
|
||||||
|
if ((new_stat ^ this->bus_stat) & 0xFF00U) {
|
||||||
|
for (mask = SCSI_CTRL_RST; mask >= SCSI_CTRL_SEL; mask >>= 1) {
|
||||||
|
if ((new_stat ^ this->bus_stat) & mask) {
|
||||||
|
if (new_stat & mask)
|
||||||
|
this->bus_obj->assert_ctrl_line(this->src_id, mask);
|
||||||
|
else
|
||||||
|
this->bus_obj->release_ctrl_line(this->src_id, mask);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
this->bus_stat = new_stat;
|
||||||
|
}
|
||||||
|
|
||||||
void MeshController::step_completed() {
|
void MeshController::step_completed() {
|
||||||
this->int_stat |= INT_CMD_DONE;
|
this->int_stat |= INT_CMD_DONE;
|
||||||
update_irq();
|
update_irq();
|
||||||
|
@ -141,6 +141,7 @@ public:
|
|||||||
protected:
|
protected:
|
||||||
void reset(bool is_hard_reset);
|
void reset(bool is_hard_reset);
|
||||||
void perform_command(const uint8_t cmd);
|
void perform_command(const uint8_t cmd);
|
||||||
|
void update_bus_status(const uint16_t new_stat);
|
||||||
|
|
||||||
private:
|
private:
|
||||||
uint8_t chip_id;
|
uint8_t chip_id;
|
||||||
|
Loading…
Reference in New Issue
Block a user