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mesh: fix writes to BusStatus0 & BusStatus1 registers.
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commit
19ecc4f945
@ -115,19 +115,11 @@ void MeshController::write(uint8_t reg_offset, uint8_t value) {
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case MeshReg::Sequence:
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perform_command(value);
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break;
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case MeshReg::BusStatus0:
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this->update_bus_status((this->bus_stat & 0xFF00U) | value);
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break;
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case MeshReg::BusStatus1:
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new_stat = value << 8;
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if (new_stat != this->bus_stat) {
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for (uint16_t mask = SCSI_CTRL_RST; mask >= SCSI_CTRL_SEL; mask >>= 1) {
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if ((new_stat ^ this->bus_stat) & mask) {
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if (new_stat & mask)
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this->bus_obj->assert_ctrl_line(this->src_id, mask);
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else
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this->bus_obj->release_ctrl_line(this->src_id, mask);
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}
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}
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this->bus_stat = new_stat;
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}
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this->update_bus_status((this->bus_stat & 0xFFU) | (value << 8));
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break;
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case MeshReg::IntMask:
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this->int_mask = value;
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@ -248,6 +240,36 @@ void MeshController::perform_command(const uint8_t cmd) {
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}
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}
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void MeshController::update_bus_status(const uint16_t new_stat) {
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uint16_t mask;
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// update the lower part (BusStatus0)
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if ((new_stat ^ this->bus_stat) & 0xFF) {
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for (mask = SCSI_CTRL_REQ; mask >= SCSI_CTRL_IO; mask >>= 1) {
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if ((new_stat ^ this->bus_stat) & mask) {
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if (new_stat & mask)
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this->bus_obj->assert_ctrl_line(this->src_id, mask);
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else
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this->bus_obj->release_ctrl_line(this->src_id, mask);
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}
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}
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}
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// update the upper part (BusStatus1)
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if ((new_stat ^ this->bus_stat) & 0xFF00U) {
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for (mask = SCSI_CTRL_RST; mask >= SCSI_CTRL_SEL; mask >>= 1) {
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if ((new_stat ^ this->bus_stat) & mask) {
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if (new_stat & mask)
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this->bus_obj->assert_ctrl_line(this->src_id, mask);
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else
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this->bus_obj->release_ctrl_line(this->src_id, mask);
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}
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}
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}
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this->bus_stat = new_stat;
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}
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void MeshController::step_completed() {
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this->int_stat |= INT_CMD_DONE;
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update_irq();
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@ -141,6 +141,7 @@ public:
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protected:
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void reset(bool is_hard_reset);
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void perform_command(const uint8_t cmd);
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void update_bus_status(const uint16_t new_stat);
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private:
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uint8_t chip_id;
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