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Continued clean-up, part 2
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dingusdev
parent
b160e38f8f
commit
29f3ffd474
@ -645,16 +645,16 @@ static void round_to_int(const uint8_t mode) {
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uint64_t ppc_result64_d;
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switch (mode & 0x3) {
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case 0:
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ppc_result64_d = (uint32_t)round_to_nearest(val_reg_b);
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ppc_result64_d = uint32_t(round_to_nearest(val_reg_b));
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break;
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case 1:
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ppc_result64_d = (uint32_t)round_to_zero(val_reg_b);
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ppc_result64_d = uint32_t(round_to_zero(val_reg_b));
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break;
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case 2:
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ppc_result64_d = (uint32_t)round_to_pos_inf(val_reg_b);
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ppc_result64_d = uint32_t(round_to_pos_inf(val_reg_b));
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break;
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case 3:
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ppc_result64_d = (uint32_t)round_to_neg_inf(val_reg_b);
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ppc_result64_d = uint32_t(round_to_neg_inf(val_reg_b));
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break;
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}
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@ -780,7 +780,7 @@ void dppc_interpreter::ppc_stfsu() {
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void dppc_interpreter::ppc_stfsx() {
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ppc_grab_regsfpsiab();
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ppc_effective_address = (reg_a) ? val_reg_a + val_reg_b : val_reg_b;
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ppc_effective_address = reg_a ? (val_reg_a + val_reg_b) : val_reg_b;
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float result = ppc_state.fpr[reg_s].dbl64_r;
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mmu_write_vmem<uint32_t>(ppc_effective_address, uint32_t(result));
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}
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@ -800,7 +800,7 @@ void dppc_interpreter::ppc_stfsux() {
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void dppc_interpreter::ppc_stfd() {
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ppc_grab_regsfpsia();
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ppc_effective_address = int32_t(int16_t(ppc_cur_instruction));
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ppc_effective_address += (reg_a) ? val_reg_a : 0;
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ppc_effective_address += reg_a ? val_reg_a : 0;
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mmu_write_vmem<uint64_t>(ppc_effective_address, ppc_state.fpr[reg_s].int64_r);
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}
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@ -818,7 +818,7 @@ void dppc_interpreter::ppc_stfdu() {
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void dppc_interpreter::ppc_stfdx() {
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ppc_grab_regsfpsiab();
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ppc_effective_address = (reg_a) ? val_reg_a + val_reg_b : val_reg_b;
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ppc_effective_address = reg_a ? (val_reg_a + val_reg_b) : val_reg_b;
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mmu_write_vmem<uint64_t>(ppc_effective_address, ppc_state.fpr[reg_s].int64_r);
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}
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@ -835,8 +835,8 @@ void dppc_interpreter::ppc_stfdux() {
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void dppc_interpreter::ppc_stfiwx() {
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ppc_grab_regsfpsiab();
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ppc_effective_address = (reg_a) ? val_reg_a + val_reg_b : val_reg_b;
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mmu_write_vmem<uint32_t>(ppc_effective_address, (uint32_t)(ppc_state.fpr[reg_s].int64_r));
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ppc_effective_address = reg_a ? (val_reg_a + val_reg_b) : val_reg_b;
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mmu_write_vmem<uint32_t>(ppc_effective_address, uint32_t(ppc_state.fpr[reg_s].int64_r));
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}
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// Floating Point Register Transfer
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@ -852,7 +852,7 @@ void dppc_interpreter::ppc_fmr() {
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void dppc_interpreter::ppc_mffs() {
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ppc_grab_regsda();
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ppc_state.fpr[reg_d].int64_r = (uint64_t)ppc_state.fpscr | 0xFFF8000000000000ULL;
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ppc_state.fpr[reg_d].int64_r = uint64_t(ppc_state.fpscr) | 0xFFF8000000000000ULL;
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if (rc_flag)
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ppc_update_cr1();
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@ -861,7 +861,7 @@ void dppc_interpreter::ppc_mffs() {
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void dppc_interpreter::ppc_mffs_601() {
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ppc_grab_regsda();
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ppc_state.fpr[reg_d].int64_r = (uint64_t)ppc_state.fpscr | 0xFFFFFFFF00000000ULL;
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ppc_state.fpr[reg_d].int64_r = uint64_t(ppc_state.fpscr) | 0xFFFFFFFF00000000ULL;
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if (rc_flag)
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ppc_update_cr1();
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@ -959,7 +959,6 @@ void dppc_interpreter::ppc_fcmpo() {
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if (std::isnan(db_test_a) || std::isnan(db_test_b)) {
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// TODO: test for SNAN operands
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// for now, assume that at least one of the operands is QNAN
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ppc_state.fpscr |= FPSCR::VXVC;
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cmp_c |= CRx_bit::CR_SO;
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}
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else if (db_test_a < db_test_b) {
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@ -973,7 +972,7 @@ void dppc_interpreter::ppc_fcmpo() {
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}
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ppc_state.fpscr = (ppc_state.fpscr & ~FPSCR::FPCC_MASK) | (cmp_c >> 16); // update FPCC
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ppc_state.cr = ((ppc_state.cr & ~(0xF0000000 >> crf_d)) | ((cmp_c) >> crf_d));
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ppc_state.cr = ((ppc_state.cr & ~(0xF0000000 >> crf_d)) | (cmp_c >> crf_d));
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}
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void dppc_interpreter::ppc_fcmpu() {
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@ -996,5 +995,5 @@ void dppc_interpreter::ppc_fcmpu() {
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}
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ppc_state.fpscr = (ppc_state.fpscr & ~FPSCR::FPCC_MASK) | (cmp_c >> 16); // update FPCC
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ppc_state.cr = ((ppc_state.cr & ~(0xF0000000 >> crf_d)) | ((cmp_c) >> crf_d));
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ppc_state.cr = ((ppc_state.cr & ~(0xF0000000UL >> crf_d)) | (cmp_c >> crf_d));
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}
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@ -371,7 +371,7 @@ void dppc_interpreter::ppc_subfme() {
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ppc_state.spr[SPR::XER] |= XER::CA;
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if (oe_flag) {
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if (ppc_result_d == ppc_result_a && (int32_t)ppc_result_d > 0)
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if (ppc_result_d == ppc_result_a && int32_t(ppc_result_d) > 0)
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ppc_state.spr[SPR::XER] |= XER::SO | XER::OV;
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else
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ppc_state.spr[SPR::XER] &= ~XER::OV;
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@ -1489,9 +1489,9 @@ void dppc_interpreter::ppc_tw() {
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reg_a = (ppc_cur_instruction >> 11) & 31;
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reg_b = (ppc_cur_instruction >> 16) & 31;
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uint32_t ppc_to = (ppc_cur_instruction >> 21) & 31;
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if (((int32_t(ppc_state.gpr[reg_a]) < (int32_t)ppc_state.gpr[reg_b]) && (ppc_to & 0x10)) ||
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((int32_t(ppc_state.gpr[reg_a]) > (int32_t)ppc_state.gpr[reg_b]) && (ppc_to & 0x08)) ||
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((int32_t(ppc_state.gpr[reg_a]) == (int32_t)ppc_state.gpr[reg_b]) && (ppc_to & 0x04)) ||
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if (((int32_t(ppc_state.gpr[reg_a]) < int32_t(ppc_state.gpr[reg_b])) && (ppc_to & 0x10)) ||
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((int32_t(ppc_state.gpr[reg_a]) > int32_t(ppc_state.gpr[reg_b])) && (ppc_to & 0x08)) ||
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((int32_t(ppc_state.gpr[reg_a]) == int32_t(ppc_state.gpr[reg_b])) && (ppc_to & 0x04)) ||
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((ppc_state.gpr[reg_a] < ppc_state.gpr[reg_b]) && (ppc_to & 0x02)) ||
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((ppc_state.gpr[reg_a] > ppc_state.gpr[reg_b]) && (ppc_to & 0x01))) {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::TRAP);
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@ -1499,7 +1499,7 @@ void dppc_interpreter::ppc_tw() {
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}
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void dppc_interpreter::ppc_twi() {
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simm = int32_t(int16_t(ppc_cur_instruction) & 0xFFFFUL);
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simm = int32_t(int16_t(ppc_cur_instruction));
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reg_a = (ppc_cur_instruction >> 16) & 0x1F;
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uint32_t ppc_to = (ppc_cur_instruction >> 21) & 0x1F;
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if (((int32_t(ppc_state.gpr[reg_a]) < simm) && (ppc_to & 0x10)) ||
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@ -1554,7 +1554,7 @@ void dppc_interpreter::ppc_dcbtst() {
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void dppc_interpreter::ppc_dcbz() {
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ppc_grab_regsdab();
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ppc_effective_address = (reg_a == 0) ? ppc_result_b : (ppc_result_a + ppc_result_b);
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ppc_effective_address = reg_a ? (ppc_result_a + ppc_result_b) : ppc_result_b;
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ppc_effective_address &= 0xFFFFFFE0UL; // align EA on a 32-byte boundary
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@ -1627,7 +1627,7 @@ void dppc_interpreter::ppc_sth() {
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#endif
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ppc_grab_regssa();
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ppc_effective_address = int32_t(int16_t(ppc_cur_instruction));
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ppc_effective_address += (reg_a > 0) ? ppc_result_a : 0;
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ppc_effective_address += reg_a ? ppc_result_a : 0;
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mmu_write_vmem<uint16_t>(ppc_effective_address, ppc_result_d);
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//mem_write_word(ppc_effective_address, ppc_result_d);
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}
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@ -1679,7 +1679,7 @@ void dppc_interpreter::ppc_sthbrx() {
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#endif
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ppc_grab_regssab();
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ppc_effective_address = reg_a ? (ppc_result_a + ppc_result_b) : ppc_result_b;
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ppc_result_d = uint32_t(uint16_t(BYTESWAP_32(ppc_result_d)));
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ppc_result_d = uint32_t(BYTESWAP_16(uint16_t(ppc_result_d)));
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mmu_write_vmem<uint16_t>(ppc_effective_address, ppc_result_d);
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//mem_write_word(ppc_effective_address, ppc_result_d);
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}
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@ -1772,7 +1772,7 @@ void dppc_interpreter::ppc_stmw() {
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#endif
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ppc_grab_regssa();
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ppc_effective_address = int32_t(int16_t(ppc_cur_instruction));
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ppc_effective_address += (reg_a > 0) ? ppc_result_a : 0;
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ppc_effective_address += reg_a ? ppc_result_a : 0;
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/* what should we do if EA is unaligned? */
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if (ppc_effective_address & 3) {
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@ -1792,7 +1792,7 @@ void dppc_interpreter::ppc_lbz() {
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#endif
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ppc_grab_regsda();
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ppc_effective_address = int32_t(int16_t(ppc_cur_instruction));
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ppc_effective_address += (reg_a > 0) ? ppc_result_a : 0;
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ppc_effective_address += reg_a ? ppc_result_a : 0;
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//ppc_result_d = mem_grab_byte(ppc_effective_address);
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ppc_result_d = mmu_read_vmem<uint8_t>(ppc_effective_address);
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ppc_store_result_regd();
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@ -1804,7 +1804,7 @@ void dppc_interpreter::ppc_lbzu() {
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#endif
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ppc_grab_regsda();
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ppc_effective_address = int32_t(int16_t(ppc_cur_instruction));
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if ((reg_a != reg_d) || (reg_a != 0)) {
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if ((reg_a != reg_d) && reg_a != 0) {
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ppc_effective_address += ppc_result_a;
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//ppc_result_d = mem_grab_byte(ppc_effective_address);
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ppc_result_d = mmu_read_vmem<uint8_t>(ppc_effective_address);
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@ -1832,7 +1832,7 @@ void dppc_interpreter::ppc_lbzux() {
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num_int_loads++;
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#endif
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ppc_grab_regsdab();
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if ((reg_a != reg_d) || (reg_a != 0)) {
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if ((reg_a != reg_d) && reg_a != 0) {
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ppc_effective_address = ppc_result_a + ppc_result_b;
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//ppc_result_d = mem_grab_byte(ppc_effective_address);
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ppc_result_d = mmu_read_vmem<uint8_t>(ppc_effective_address);
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@ -1862,7 +1862,7 @@ void dppc_interpreter::ppc_lhzu() {
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num_int_loads++;
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#endif
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ppc_grab_regsda();
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if ((reg_a != reg_d) || (reg_a != 0)) {
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if ((reg_a != reg_d) && reg_a != 0) {
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ppc_effective_address = int32_t(int16_t(ppc_cur_instruction));
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ppc_effective_address += ppc_result_a;
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//ppc_result_d = mem_grab_word(ppc_effective_address);
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@ -1891,7 +1891,7 @@ void dppc_interpreter::ppc_lhzux() {
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num_int_loads++;
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#endif
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ppc_grab_regsdab();
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if ((reg_a != reg_d) || (reg_a != 0)) {
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if ((reg_a != reg_d) && reg_a != 0) {
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ppc_effective_address = ppc_result_a + ppc_result_b;
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//ppc_result_d = mem_grab_word(ppc_effective_address);
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ppc_result_d = mmu_read_vmem<uint16_t>(ppc_effective_address);
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@ -1921,7 +1921,7 @@ void dppc_interpreter::ppc_lhau() {
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num_int_loads++;
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#endif
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ppc_grab_regsda();
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if ((reg_a != reg_d) || (reg_a != 0)) {
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if ((reg_a != reg_d) && reg_a != 0) {
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ppc_effective_address = int32_t(int16_t(ppc_cur_instruction));
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ppc_effective_address += ppc_result_a;
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//uint16_t val = mem_grab_word(ppc_effective_address);
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@ -1940,7 +1940,7 @@ void dppc_interpreter::ppc_lhaux() {
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num_int_loads++;
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#endif
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ppc_grab_regsdab();
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if ((reg_a != reg_d) || (reg_a != 0)) {
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if ((reg_a != reg_d) && reg_a != 0) {
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ppc_effective_address = ppc_result_a + ppc_result_b;
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// uint16_t val = mem_grab_word(ppc_effective_address);
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int16_t val = mmu_read_vmem<uint16_t>(ppc_effective_address);
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@ -2006,7 +2006,7 @@ void dppc_interpreter::ppc_lwzu() {
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#endif
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ppc_grab_regsda();
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ppc_effective_address = int32_t(int16_t(ppc_cur_instruction));
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if ((reg_a != reg_d) || (reg_a != 0)) {
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if ((reg_a != reg_d) && reg_a != 0) {
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ppc_effective_address += ppc_result_a;
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//ppc_result_d = mem_grab_dword(ppc_effective_address);
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ppc_result_d = mmu_read_vmem<uint32_t>(ppc_effective_address);
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@ -2034,7 +2034,7 @@ void dppc_interpreter::ppc_lwzux() {
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num_int_loads++;
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#endif
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ppc_grab_regsdab();
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if ((reg_a != reg_d) || (reg_a != 0)) {
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if ((reg_a != reg_d) && reg_a != 0) {
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ppc_effective_address = ppc_result_a + ppc_result_b;
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// ppc_result_d = mem_grab_dword(ppc_effective_address);
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ppc_result_d = mmu_read_vmem<uint32_t>(ppc_effective_address);
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