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https://github.com/dingusdev/dingusppc.git
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ppcmmu.c: restructure and clean up.
This commit is contained in:
Maxim Poliakovski
parent
c5f45c6f9a
commit
2a79c9a63c
@ -19,7 +19,7 @@ You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file PowerPC Memory management unit emulation. */
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/** @file PowerPC Memory Management Unit emulation. */
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/* TODO:
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- implement TLB
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@ -181,13 +181,6 @@ public:
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};
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#endif
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/** Temporary TLB test variables. */
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bool MemAccessType; // true - memory, false - I/O
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bool Unaligned_crosspage = false;
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uint64_t MemAddr = 0;
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MMIODevice *Device = 0;
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uint32_t DevOffset = 0;
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/** remember recently used physical memory regions for quicker translation. */
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AddressMapEntry last_read_area = {0xFFFFFFFF, 0xFFFFFFFF};
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@ -215,16 +208,6 @@ static inline T read_phys_mem(AddressMapEntry *mru_rgn, uint32_t addr)
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dmem_reads_total++;
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#endif
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if (!MemAccessType) {
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LOG_F(ERROR, "TLB real memory access expected!");
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}
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if ((mru_rgn->mem_ptr + (addr - mru_rgn->start)) != (uint8_t *)MemAddr) {
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LOG_F(ERROR, "TLB address mismatch! Expected: 0x%llx, got: 0x%llx",
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(uint64_t)(mru_rgn->mem_ptr + (addr - mru_rgn->start)),
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(uint64_t)MemAddr);
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}
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switch(sizeof(T)) {
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case 1:
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return *(mru_rgn->mem_ptr + (addr - mru_rgn->start));
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@ -252,14 +235,6 @@ static inline T read_phys_mem(AddressMapEntry *mru_rgn, uint32_t addr)
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#ifdef MMU_PROFILING
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iomem_reads_total++;
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#endif
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if (MemAccessType) {
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LOG_F(ERROR, "TLB I/O memory access expected!");
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}
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if (mru_rgn->devobj != Device || (addr - mru_rgn->start) != DevOffset) {
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LOG_F(ERROR, "TLB MMIO access mismatch! Expected: 0x%X, got: 0x%X",
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addr - mru_rgn->start, DevOffset);
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}
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return (mru_rgn->devobj->read(mru_rgn->start,
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addr - mru_rgn->start, sizeof(T)));
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@ -287,20 +262,6 @@ static inline void write_phys_mem(AddressMapEntry *mru_rgn, uint32_t addr, T val
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dmem_writes_total++;
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#endif
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#if 1
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if (!MemAccessType) {
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LOG_F(ERROR, "TLB real memory access expected!");
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}
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if (!is_aligned && Unaligned_crosspage) {
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LOG_F(WARNING, "Unaligned cross-page access ignored!");
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} else if ((mru_rgn->mem_ptr + (addr - mru_rgn->start)) != (uint8_t *)MemAddr) {
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LOG_F(ERROR, "TLB address mismatch! Expected: 0x%llx, got: 0x%llx",
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(uint64_t)(mru_rgn->mem_ptr + (addr - mru_rgn->start)),
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(uint64_t)MemAddr);
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}
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#endif
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switch(sizeof(T)) {
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case 1:
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*(mru_rgn->mem_ptr + (addr - mru_rgn->start)) = value;
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@ -333,17 +294,6 @@ static inline void write_phys_mem(AddressMapEntry *mru_rgn, uint32_t addr, T val
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iomem_writes_total++;
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#endif
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#if 1
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if (MemAccessType) {
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LOG_F(ERROR, "TLB I/O memory access expected!");
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}
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if (mru_rgn->devobj != Device || (addr - mru_rgn->start) != DevOffset) {
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LOG_F(ERROR, "TLB MMIO access mismatch! Expected: 0x%X, got: 0x%X",
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addr - mru_rgn->start, DevOffset);
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}
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#endif
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mru_rgn->devobj->write(mru_rgn->start, addr - mru_rgn->start, value,
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sizeof(T));
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} else {
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@ -375,6 +325,10 @@ void ppc_set_cur_instruction(const uint8_t* ptr) {
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bool gTLBFlushBatEntries = false;
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bool gTLBFlushPatEntries = false;
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// Forward declarations.
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void tlb_flush_bat_entries();
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void tlb_flush_pat_entries();
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void ibat_update(uint32_t bat_reg) {
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int upper_reg_num;
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uint32_t bl, hi_mask;
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@ -527,7 +481,7 @@ static bool search_pteg(
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return false;
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}
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static PATResult page_address_translate(uint32_t la, bool is_instr_fetch,
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static PATResult page_address_translation(uint32_t la, bool is_instr_fetch,
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unsigned msr_pr, int is_write)
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{
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uint32_t sr_val, page_index, pteg_hash1, vsid, pte_word2;
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@ -598,7 +552,7 @@ static PATResult page_address_translate(uint32_t la, bool is_instr_fetch,
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}
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/** PowerPC-style MMU instruction address translation. */
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static uint32_t ppc_mmu_instr_translate(uint32_t la) {
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static uint32_t mmu_instr_translation(uint32_t la) {
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uint32_t pa; /* translated physical address */
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bool bat_hit = false;
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@ -631,7 +585,7 @@ static uint32_t ppc_mmu_instr_translate(uint32_t la) {
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/* page address translation */
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if (!bat_hit) {
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PATResult pat_res = page_address_translate(la, true, msr_pr, 0);
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PATResult pat_res = page_address_translation(la, true, msr_pr, 0);
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pa = pat_res.phys;
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#ifdef MMU_PROFILING
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@ -678,7 +632,7 @@ static uint32_t ppc_mmu_addr_translate(uint32_t la, int is_write) {
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/* page address translation */
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if (!bat_hit) {
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PATResult pat_res = page_address_translate(la, false, msr_pr, is_write);
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PATResult pat_res = page_address_translation(la, false, msr_pr, is_write);
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pa = pat_res.phys;
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#ifdef MMU_PROFILING
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@ -812,7 +766,7 @@ static TLBEntry* tlb2_target_entry(uint32_t gp_va)
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tlb_entry[2].lru_bits = 0x2;
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tlb_entry[3].lru_bits = 0x3;
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return &tlb_entry[3];
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} else { // no invalid blocks, replace an existing one according with the hLRU policy
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} else { // no free entries, replace an existing one according with the hLRU policy
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#ifdef TLB_PROFILING
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num_entry_replacements++;
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#endif
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@ -880,7 +834,7 @@ static TLBEntry* tlb2_refill(uint32_t guest_va, int is_write)
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}
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} else {
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// page address translation
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PATResult pat_res = page_address_translate(guest_va, false,
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PATResult pat_res = page_address_translation(guest_va, false,
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!!(ppc_state.msr & 0x4000), is_write);
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phys_addr = pat_res.phys;
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flags = TLBFlags::TLBE_FROM_PAT; // tell the world we come from
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@ -1018,8 +972,6 @@ static inline uint64_t tlb_translate_addr(uint32_t guest_va)
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// look up address in the primary TLB
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tlb1_entry = &pCurTLB1[(guest_va >> PAGE_SIZE_BITS) & tlb_size_mask];
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if (tlb1_entry->tag == tag) { // primary TLB hit -> fast path
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MemAccessType = true;
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MemAddr = tlb1_entry->host_va_offset + guest_va;
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return tlb1_entry->host_va_offset + guest_va;
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} else { // primary TLB miss -> look up address in the secondary TLB
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tlb2_entry = &pCurTLB2[((guest_va >> PAGE_SIZE_BITS) & tlb_size_mask) * TLB2_WAYS];
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@ -1060,13 +1012,8 @@ static inline uint64_t tlb_translate_addr(uint32_t guest_va)
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tlb1_entry->tag = tag;
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tlb1_entry->flags = tlb2_entry->flags;
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tlb1_entry->host_va_offset = tlb2_entry->host_va_offset;
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MemAccessType = true;
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MemAddr = tlb1_entry->host_va_offset + guest_va;
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return tlb1_entry->host_va_offset + guest_va;
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} else { // an attempt to access a memory-mapped device
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MemAccessType = false;
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Device = tlb2_entry->reg_desc->devobj;
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DevOffset = guest_va - tlb2_entry->reg_desc->start;
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return guest_va - tlb2_entry->reg_desc->start;
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}
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}
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@ -1236,7 +1183,6 @@ inline T mmu_read_vmem(uint32_t guest_va) {
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}
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// explicitely instantiate all required mmu_read_vmem variants
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// to avoid linking errors
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template uint8_t mmu_read_vmem<uint8_t>(uint32_t guest_va);
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template uint16_t mmu_read_vmem<uint16_t>(uint32_t guest_va);
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template uint32_t mmu_read_vmem<uint32_t>(uint32_t guest_va);
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@ -1262,7 +1208,7 @@ inline void mmu_write_vmem(uint32_t guest_va, T value) {
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}
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if (!(tlb1_entry->flags & TLBFlags::PTE_SET_C)) {
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// perform full page address translation to update PTE.C bit
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PATResult pat_res = page_address_translate(guest_va, false,
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PATResult pat_res = page_address_translation(guest_va, false,
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!!(ppc_state.msr & 0x4000), true);
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tlb1_entry->flags |= TLBFlags::PTE_SET_C;
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@ -1273,8 +1219,6 @@ inline void mmu_write_vmem(uint32_t guest_va, T value) {
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}
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}
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host_va = (uint8_t *)(tlb1_entry->host_va_offset + guest_va);
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MemAccessType = true;
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MemAddr = (uint64_t)host_va;
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} else {
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// primary TLB miss -> look up address in the secondary TLB
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tlb2_entry = lookup_secondary_tlb(guest_va, tag);
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@ -1293,8 +1237,6 @@ inline void mmu_write_vmem(uint32_t guest_va, T value) {
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#endif
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if (!(tlb2_entry->flags & TLBFlags::PAGE_WRITABLE)) {
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LOG_F(WARNING, "DSI Exception in mmu_write_vmem! PC=0x%08X", ppc_state.pc);
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//return;
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ppc_state.spr[SPR::DSISR] = 0x08000000 | (1 << 25);
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ppc_state.spr[SPR::DAR] = guest_va;
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mmu_exception_handler(Except_Type::EXC_DSI, 0);
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@ -1302,7 +1244,7 @@ inline void mmu_write_vmem(uint32_t guest_va, T value) {
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if (!(tlb2_entry->flags & TLBFlags::PTE_SET_C)) {
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// perform full page address translation to update PTE.C bit
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PATResult pat_res = page_address_translate(guest_va, false,
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PATResult pat_res = page_address_translation(guest_va, false,
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!!(ppc_state.msr & 0x4000), true);
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tlb2_entry->flags |= TLBFlags::PTE_SET_C;
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}
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@ -1313,17 +1255,12 @@ inline void mmu_write_vmem(uint32_t guest_va, T value) {
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tlb1_entry->flags = tlb2_entry->flags;
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tlb1_entry->host_va_offset = tlb2_entry->host_va_offset;
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host_va = (uint8_t *)(tlb1_entry->host_va_offset + guest_va);
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//MemAccessType = true;
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//MemAddr = (uint64_t)host_va;
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} else { // otherwise, it's an access to a memory-mapped device
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#ifdef MMU_PROFILING
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iomem_writes_total++;
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#endif
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tlb2_entry->reg_desc->devobj->write(tlb2_entry->reg_desc->start,
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guest_va - tlb2_entry->reg_desc->start, value, sizeof(T));
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//MemAccessType = false;
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//Device = tlb2_entry->reg_desc->devobj;
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//DevOffset = guest_va - tlb2_entry->reg_desc->start;
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return;
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}
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}
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@ -1338,7 +1275,6 @@ inline void mmu_write_vmem(uint32_t guest_va, T value) {
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return;
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}
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#if 1
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// handle aligned memory accesses
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switch(sizeof(T)) {
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case 1:
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@ -1354,11 +1290,9 @@ inline void mmu_write_vmem(uint32_t guest_va, T value) {
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WRITE_QWORD_BE_A(host_va, value);
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break;
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}
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#endif
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}
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// explicitely instantiate all required mmu_write_vmem variants
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// to avoid linking errors
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template void mmu_write_vmem<uint8_t>(uint32_t guest_va, uint8_t value);
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template void mmu_write_vmem<uint16_t>(uint32_t guest_va, uint16_t value);
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template void mmu_write_vmem<uint32_t>(uint32_t guest_va, uint32_t value);
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@ -1556,7 +1490,7 @@ uint8_t* quickinstruction_translate(uint32_t addr) {
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/* perform instruction address translation if enabled */
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if (ppc_state.msr & 0x20) {
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addr = ppc_mmu_instr_translate(addr);
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addr = mmu_instr_translation(addr);
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}
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if (addr >= last_exec_area.start && addr <= last_exec_area.end) {
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@ -19,10 +19,10 @@ You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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// The opcodes for the processor - ppcopcodes.cpp
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/** @file PowerPC Memory Management Unit definitions. */
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#ifndef PPCMEMORY_H
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#define PPCMEMORY_H
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#ifndef PPCMMU_H
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#define PPCMMU_H
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#include <array>
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#include <cinttypes>
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@ -93,8 +93,6 @@ extern uint8_t* mmu_get_dma_mem(uint32_t addr, uint32_t size);
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extern void mmu_change_mode(void);
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extern void mmu_pat_ctx_changed();
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extern void tlb_flush_entry(uint32_t ea);
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extern void tlb_flush_bat_entries();
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extern void tlb_flush_pat_entries();
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extern void ppc_set_cur_instruction(const uint8_t* ptr);
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extern void mem_write_byte(uint32_t addr, uint8_t value);
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@ -113,4 +111,4 @@ extern T mmu_read_vmem(uint32_t guest_va);
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template <class T>
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extern void mmu_write_vmem(uint32_t guest_va, T value);
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#endif // PPCMEMORY_H
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#endif // PPCMMU_H
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@ -873,7 +873,6 @@ void dppc_interpreter::ppc_mtspr() {
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}
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if (ref_spr == SPR::SDR1) {
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LOG_F(INFO, "SDR1 changed to 0x%08X", ppc_state.spr[SPR::SDR1]);
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mmu_pat_ctx_changed();
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}
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