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ppcfpopcodes: fix fmul emulation.
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2539faef7e
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@ -490,7 +490,7 @@ extern void ppc_stfdux();
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extern void ppc_fadd();
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extern void ppc_fsub();
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extern void ppc_fmult();
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extern void ppc_fmul();
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extern void ppc_fdiv();
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extern void ppc_fadds();
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extern void ppc_fsubs();
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@ -656,7 +656,7 @@ void initialize_ppc_opcode_tables() {
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}
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for (int i = 25; i < 1024; i += 32) {
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SubOpcode63Grabber[i] = ppc_fmult;
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SubOpcode63Grabber[i] = ppc_fmul;
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}
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for (int i = 28; i < 1024; i += 32) {
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@ -61,20 +61,16 @@ uint64_t fp_return_uint64(uint32_t reg) {
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void ppc_store_sfpresult(bool int_rep) {
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if (int_rep) {
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ppc_state.fpr[reg_d].int64_r = ppc_result64_d;
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ppc_state.fpr[reg_d].dbl64_r = *(double*)&ppc_result64_d;
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} else {
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ppc_state.fpr[reg_d].dbl64_r = ppc_dblresult64_d;
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ppc_state.fpr[reg_d].int64_r = *(uint64_t*)&ppc_dblresult64_d;
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}
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}
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void ppc_store_dfpresult(bool int_rep) {
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if (int_rep) {
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ppc_state.fpr[reg_d].int64_r = ppc_result64_d;
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ppc_state.fpr[reg_d].dbl64_r = *(double*)&ppc_result64_d;
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} else {
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ppc_state.fpr[reg_d].dbl64_r = ppc_dblresult64_d;
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ppc_state.fpr[reg_d].int64_r = *(uint64_t*)&ppc_dblresult64_d;
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}
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}
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@ -407,11 +403,11 @@ void dppc_interpreter::ppc_fdiv() {
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ppc_changecrf1();
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}
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void dppc_interpreter::ppc_fmult() {
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void dppc_interpreter::ppc_fmul() {
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ppc_grab_regsfpdac(false);
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if (!ppc_confirm_inf_nan(reg_a, reg_b, false, 50)) {
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ppc_dblresult64_d = ppc_dblresult64_a * ppc_dblresult64_b;
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ppc_dblresult64_d = ppc_dblresult64_a * ppc_dblresult64_c;
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ppc_store_dfpresult(false);
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}
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