Macintosh-Tools/dingusppc
1
0
Fork 0
mirror of https://github.com/dingusdev/dingusppc.git synced 2025-01-11 05:29:43 +00:00
Code Issues Projects Releases Wiki Activity

Fix read/write argument names

Browse Source 
base class uses reg_start so derived classes should do the same.
Some derived class already uses reg_start for read method.
This commit is contained in:
joevt 2022-08-22 03:16:31 -07:00
parent 3b4f40635a
commit 3ee2ea1871
21 changed files with 56 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
devices/common/machineid.h
View File

@ -55,12 +55,12 @@ public:
}; };
~NubusMacID() = default; ~NubusMacID() = default;
uint32_t read(uint32_t reg_start, uint32_t offset, int size) { uint32_t read(uint32_t rgn_start, uint32_t offset, int size) {
return (offset < 4 ? this->id[offset] : 0); return (offset < 4 ? this->id[offset] : 0);
}; };
/* not writable */ /* not writable */
void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) {}; void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) {};
private: private:
uint8_t id[4]; uint8_t id[4];
@ -80,12 +80,12 @@ public:
}; };
~GossamerID() = default; ~GossamerID() = default;
uint32_t read(uint32_t reg_start, uint32_t offset, int size) { uint32_t read(uint32_t rgn_start, uint32_t offset, int size) {
return ((!offset && size == 2) ? this->id : 0); return ((!offset && size == 2) ? this->id : 0);
}; };
/* not writable */ /* not writable */
void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) {}; void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) {};
private: private:
uint16_t id; uint16_t id;

4
devices/common/mmiodevice.h
View File

@ -31,8 +31,8 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
class MMIODevice : public HWComponent { class MMIODevice : public HWComponent {
public: public:
MMIODevice() = default; MMIODevice() = default;
virtual uint32_t read(uint32_t reg_start, uint32_t offset, int size) = 0; virtual uint32_t read(uint32_t rgn_start, uint32_t offset, int size) = 0;
virtual void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) = 0; virtual void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) = 0;
virtual ~MMIODevice() = default; virtual ~MMIODevice() = default;
}; };

8
devices/common/pci/bandit.cpp
View File

@ -111,7 +111,7 @@ void Bandit::pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size)
} }
} }
uint32_t Bandit::read(uint32_t reg_start, uint32_t offset, int size) uint32_t Bandit::read(uint32_t rgn_start, uint32_t offset, int size)
{ {
int bus_num, dev_num, fun_num; int bus_num, dev_num, fun_num;
uint8_t reg_offs; uint8_t reg_offs;
@ -178,7 +178,7 @@ uint32_t Bandit::read(uint32_t reg_start, uint32_t offset, int size)
return result; return result;
} }
void Bandit::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) void Bandit::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
{ {
int bus_num, dev_num, fun_num; int bus_num, dev_num, fun_num;
uint8_t reg_offs; uint8_t reg_offs;
@ -284,7 +284,7 @@ Chaos::Chaos(std::string name) : PCIHost()
this->name = name; this->name = name;
} }
uint32_t Chaos::read(uint32_t reg_start, uint32_t offset, int size) uint32_t Chaos::read(uint32_t rgn_start, uint32_t offset, int size)
{ {
int bus_num, dev_num, fun_num; int bus_num, dev_num, fun_num;
uint8_t reg_offs; uint8_t reg_offs;
@ -340,7 +340,7 @@ uint32_t Chaos::read(uint32_t reg_start, uint32_t offset, int size)
return result; return result;
} }
void Chaos::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) void Chaos::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
{ {
int bus_num, dev_num, fun_num; int bus_num, dev_num, fun_num;
uint8_t reg_offs; uint8_t reg_offs;

8
devices/common/pci/bandit.h
View File

@ -63,8 +63,8 @@ public:
void pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size); void pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size);
// MMIODevice methods // MMIODevice methods
uint32_t read(uint32_t reg_start, uint32_t offset, int size); uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size); void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
protected: protected:
void verbose_address_space(); void verbose_address_space();
@ -90,8 +90,8 @@ public:
}; };
// MMIODevice methods // MMIODevice methods
uint32_t read(uint32_t reg_start, uint32_t offset, int size); uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size); void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
private: private:
std::string name; std::string name;

4
devices/ioctrl/amic.cpp
View File

@ -101,7 +101,7 @@ int AMIC::device_postinit()
return 0; return 0;
} }
uint32_t AMIC::read(uint32_t reg_start, uint32_t offset, int size) uint32_t AMIC::read(uint32_t rgn_start, uint32_t offset, int size)
{ {
uint32_t phase_val; uint32_t phase_val;
@ -180,7 +180,7 @@ uint32_t AMIC::read(uint32_t reg_start, uint32_t offset, int size)
return 0; return 0;
} }
void AMIC::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) void AMIC::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
{ {
uint32_t mask; uint32_t mask;

4
devices/ioctrl/amic.h
View File

@ -192,8 +192,8 @@ public:
int device_postinit(); int device_postinit();
/* MMIODevice methods */ /* MMIODevice methods */
uint32_t read(uint32_t reg_start, uint32_t offset, int size); uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size); void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
// InterruptCtrl methods // InterruptCtrl methods
uint32_t register_dev_int(IntSrc src_id); uint32_t register_dev_int(IntSrc src_id);

4
devices/ioctrl/grandcentral.cpp
View File

@ -94,7 +94,7 @@ void GrandCentral::notify_bar_change(int bar_num)
} }
} }
uint32_t GrandCentral::read(uint32_t reg_start, uint32_t offset, int size) uint32_t GrandCentral::read(uint32_t rgn_start, uint32_t offset, int size)
{ {
if (offset & 0x10000) { // Device register space if (offset & 0x10000) { // Device register space
unsigned subdev_num = (offset >> 12) & 0xF; unsigned subdev_num = (offset >> 12) & 0xF;
@ -160,7 +160,7 @@ uint32_t GrandCentral::read(uint32_t reg_start, uint32_t offset, int size)
return 0; return 0;
} }
void GrandCentral::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) void GrandCentral::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
{ {
if (offset & 0x10000) { // Device register space if (offset & 0x10000) { // Device register space
unsigned subdev_num = (offset >> 12) & 0xF; unsigned subdev_num = (offset >> 12) & 0xF;

4
devices/ioctrl/heathrow.cpp
View File

@ -128,7 +128,7 @@ void HeathrowIC::dma_write(uint32_t offset, uint32_t value, int size) {
} }
uint32_t HeathrowIC::read(uint32_t reg_start, uint32_t offset, int size) { uint32_t HeathrowIC::read(uint32_t rgn_start, uint32_t offset, int size) {
uint32_t res = 0; uint32_t res = 0;
LOG_F(9, "%s: reading from offset %x", this->name.c_str(), offset); LOG_F(9, "%s: reading from offset %x", this->name.c_str(), offset);
@ -172,7 +172,7 @@ uint32_t HeathrowIC::read(uint32_t reg_start, uint32_t offset, int size) {
return res; return res;
} }
void HeathrowIC::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) { void HeathrowIC::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) {
LOG_F(9, "%s: writing to offset %x", this->name.c_str(), offset); LOG_F(9, "%s: writing to offset %x", this->name.c_str(), offset);
unsigned sub_addr = (offset >> 12) & 0x7F; unsigned sub_addr = (offset >> 12) & 0x7F;

8
devices/ioctrl/macio.h
View File

@ -100,8 +100,8 @@ public:
} }
// MMIO device methods // MMIO device methods
uint32_t read(uint32_t reg_start, uint32_t offset, int size); uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size); void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
// InterruptCtrl methods // InterruptCtrl methods
uint32_t register_dev_int(IntSrc src_id); uint32_t register_dev_int(IntSrc src_id);
@ -182,8 +182,8 @@ public:
} }
// MMIO device methods // MMIO device methods
uint32_t read(uint32_t reg_start, uint32_t offset, int size); uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size); void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
// InterruptCtrl methods // InterruptCtrl methods
uint32_t register_dev_int(IntSrc src_id); uint32_t register_dev_int(IntSrc src_id);

2
devices/memctrl/hammerhead.cpp
View File

@ -40,7 +40,7 @@ HammerheadCtrl::HammerheadCtrl() : MemCtrlBase()
add_mmio_region(0xF8000000, 0x500, this); add_mmio_region(0xF8000000, 0x500, this);
} }
uint32_t HammerheadCtrl::read(uint32_t reg_start, uint32_t offset, int size) uint32_t HammerheadCtrl::read(uint32_t rgn_start, uint32_t offset, int size)
{ {
uint32_t result; uint32_t result;

2
devices/memctrl/hammerhead.h
View File

@ -97,7 +97,7 @@ public:
} }
// MMIODevice methods // MMIODevice methods
uint32_t read(uint32_t reg_start, uint32_t offset, int size); uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size); void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
void insert_ram_dimm(int slot_num, uint32_t capacity); void insert_ram_dimm(int slot_num, uint32_t capacity);

4
devices/memctrl/hmc.cpp
View File

@ -41,7 +41,7 @@ HMC::HMC() : MemCtrlBase()
this->bit_pos = 0; this->bit_pos = 0;
} }
uint32_t HMC::read(uint32_t reg_start, uint32_t offset, int size) uint32_t HMC::read(uint32_t rgn_start, uint32_t offset, int size)
{ {
if (!offset) if (!offset)
return !!(this->ctrl_reg & (1ULL << this->bit_pos++)); return !!(this->ctrl_reg & (1ULL << this->bit_pos++));
@ -49,7 +49,7 @@ uint32_t HMC::read(uint32_t reg_start, uint32_t offset, int size)
return 0; /* FIXME: what should be returned for invalid offsets? */ return 0; /* FIXME: what should be returned for invalid offsets? */
} }
void HMC::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) void HMC::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
{ {
uint64_t bit; uint64_t bit;

4
devices/memctrl/hmc.h
View File

@ -51,8 +51,8 @@ public:
} }
/* MMIODevice methods */ /* MMIODevice methods */
uint32_t read(uint32_t reg_start, uint32_t offset, int size); uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size); void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
uint64_t get_control_reg(void) { uint64_t get_control_reg(void) {
return this->ctrl_reg; return this->ctrl_reg;

8
devices/memctrl/mpc106.cpp
View File

@ -74,10 +74,10 @@ int MPC106::device_postinit()
return 0; return 0;
} }
uint32_t MPC106::read(uint32_t reg_start, uint32_t offset, int size) { uint32_t MPC106::read(uint32_t rgn_start, uint32_t offset, int size) {
uint32_t result; uint32_t result;
if (reg_start == 0xFE000000) { if (rgn_start == 0xFE000000) {
// broadcast I/O request to devices that support I/O space // broadcast I/O request to devices that support I/O space
// until a device returns true that means "request accepted" // until a device returns true that means "request accepted"
for (auto& dev : this->io_space_devs) { for (auto& dev : this->io_space_devs) {
@ -98,8 +98,8 @@ uint32_t MPC106::read(uint32_t reg_start, uint32_t offset, int size) {
return 0; return 0;
} }
void MPC106::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) { void MPC106::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) {
if (reg_start == 0xFE000000) { if (rgn_start == 0xFE000000) {
// broadcast I/O request to devices that support I/O space // broadcast I/O request to devices that support I/O space
// until a device returns true that means "request accepted" // until a device returns true that means "request accepted"
for (auto& dev : this->io_space_devs) { for (auto& dev : this->io_space_devs) {

4
devices/memctrl/mpc106.h
View File

@ -52,8 +52,8 @@ public:
return std::unique_ptr<MPC106>(new MPC106()); return std::unique_ptr<MPC106>(new MPC106());
} }
uint32_t read(uint32_t reg_start, uint32_t offset, int size); uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size); void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
int device_postinit(); int device_postinit();

2
devices/memctrl/platinum.cpp
View File

@ -53,7 +53,7 @@ PlatinumCtrl::PlatinumCtrl() : MemCtrlBase()
this->display_id = std::unique_ptr<DisplayID> (new DisplayID()); this->display_id = std::unique_ptr<DisplayID> (new DisplayID());
} }
uint32_t PlatinumCtrl::read(uint32_t reg_start, uint32_t offset, int size) uint32_t PlatinumCtrl::read(uint32_t rgn_start, uint32_t offset, int size)
{ {
if (size != 4) { if (size != 4) {
LOG_F(WARNING, "Platinum: unsupported register access size %d!", size); LOG_F(WARNING, "Platinum: unsupported register access size %d!", size);

2
devices/memctrl/platinum.h
View File

@ -155,7 +155,7 @@ public:
} }
/* MMIODevice methods */ /* MMIODevice methods */
uint32_t read(uint32_t reg_start, uint32_t offset, int size); uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size); void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
void insert_ram_dimm(int slot_num, uint32_t capacity); void insert_ram_dimm(int slot_num, uint32_t capacity);

12
devices/video/atirage.cpp
View File

@ -378,11 +378,11 @@ bool ATIRage::pci_io_write(uint32_t offset, uint32_t value, uint32_t size) {
} }
uint32_t ATIRage::read(uint32_t reg_start, uint32_t offset, int size) uint32_t ATIRage::read(uint32_t rgn_start, uint32_t offset, int size)
{ {
LOG_F(8, "Reading ATI Rage PCI memory: region=%X, offset=%X, size %d", reg_start, offset, size); LOG_F(8, "Reading ATI Rage PCI memory: region=%X, offset=%X, size %d", rgn_start, offset, size);
if (reg_start < this->aperture_base || offset > APERTURE_SIZE) { if (rgn_start < this->aperture_base || offset > APERTURE_SIZE) {
LOG_F(WARNING, "ATI Rage: attempt to read outside the aperture!"); LOG_F(WARNING, "ATI Rage: attempt to read outside the aperture!");
return 0; return 0;
} }
@ -410,11 +410,11 @@ uint32_t ATIRage::read(uint32_t reg_start, uint32_t offset, int size)
return 0; return 0;
} }
void ATIRage::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) void ATIRage::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
{ {
LOG_F(8, "Writing reg=%X, offset=%X, value=%X, size %d", reg_start, offset, value, size); LOG_F(8, "Writing reg=%X, offset=%X, value=%X, size %d", rgn_start, offset, value, size);
if (reg_start < this->aperture_base || offset > APERTURE_SIZE) { if (rgn_start < this->aperture_base || offset > APERTURE_SIZE) {
LOG_F(WARNING, "ATI Rage: attempt to write outside the aperture!"); LOG_F(WARNING, "ATI Rage: attempt to write outside the aperture!");
return; return;
} }

4
devices/video/atirage.h
View File

@ -56,8 +56,8 @@ public:
} }
/* MMIODevice methods */ /* MMIODevice methods */
uint32_t read(uint32_t reg_start, uint32_t offset, int size); uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size); void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
/* PCI device methods */ /* PCI device methods */
bool supports_io_space(void) { bool supports_io_space(void) {

12
devices/video/control.cpp
View File

@ -103,11 +103,11 @@ void ControlVideo::notify_bar_change(int bar_num)
} }
} }
uint32_t ControlVideo::read(uint32_t reg_start, uint32_t offset, int size) uint32_t ControlVideo::read(uint32_t rgn_start, uint32_t offset, int size)
{ {
uint32_t result = 0; uint32_t result = 0;
if (reg_start == this->vram_base) { if (rgn_start == this->vram_base) {
if (offset >= 0x800000) { if (offset >= 0x800000) {
return read_mem_rev(&this->vram_ptr[offset - 0x800000], size); return read_mem_rev(&this->vram_ptr[offset - 0x800000], size);
} else { } else {
@ -124,15 +124,15 @@ uint32_t ControlVideo::read(uint32_t reg_start, uint32_t offset, int size)
result = this->cur_mon_id << 6; result = this->cur_mon_id << 6;
break; break;
default: default:
LOG_F(INFO, "read from 0x%08X:0x%08X", reg_start, offset); LOG_F(INFO, "read from 0x%08X:0x%08X", rgn_start, offset);
} }
return BYTESWAP_32(result); return BYTESWAP_32(result);
} }
void ControlVideo::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) void ControlVideo::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
{ {
if (reg_start == this->vram_base) { if (rgn_start == this->vram_base) {
if (offset >= 0x800000) { if (offset >= 0x800000) {
write_mem_rev(&this->vram_ptr[offset - 0x800000], value, size); write_mem_rev(&this->vram_ptr[offset - 0x800000], value, size);
} else { } else {
@ -209,7 +209,7 @@ void ControlVideo::write(uint32_t reg_start, uint32_t offset, uint32_t value, in
this->int_enable = value; this->int_enable = value;
break; break;
default: default:
LOG_F(INFO, "write 0x%08X to 0x%08X:0x%08X", value, reg_start, offset); LOG_F(INFO, "write 0x%08X to 0x%08X:0x%08X", value, rgn_start, offset);
} }
} }

4
devices/video/control.h
View File

@ -97,8 +97,8 @@ public:
} }
// MMIODevice methods // MMIODevice methods
uint32_t read(uint32_t reg_start, uint32_t offset, int size); uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size); void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
protected: protected:
void notify_bar_change(int bar_num); void notify_bar_change(int bar_num);