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heathrow: implement floppy DMA interrupts.
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57ea3c2e66
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@ -91,6 +91,7 @@ HeathrowIC::HeathrowIC() : PCIDevice("mac-io/heathrow"), InterruptCtrl()
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this->swim3 = dynamic_cast<Swim3::Swim3Ctrl*>(gMachineObj->get_comp_by_name("Swim3"));
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this->floppy_dma = std::unique_ptr<DMAChannel> (new DMAChannel());
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this->swim3->set_dma_channel(this->floppy_dma.get());
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this->floppy_dma->register_dma_int(this, 2);
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// set EMMO pin status (active low)
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this->emmo_pin = GET_BIN_PROP("emmo") ^ 1;
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@ -259,6 +260,11 @@ uint32_t HeathrowIC::mio_ctrl_read(uint32_t offset, int size) {
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case MIO_INT_LEVELS1:
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res = this->int_levels1;
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break;
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case MIO_INT_CLEAR1:
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case MIO_INT_CLEAR2:
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// some Mac OS drivers reads from those write-only registers
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// so we return zero here as real HW does
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break;
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case MIO_OHARE_ID:
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LOG_F(9, "read from MIO:ID register at Address %x", ppc_state.pc);
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res = (this->fp_id << 24) | (this->mon_id << 16) | (this->mb_id << 8) |
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@ -375,23 +381,38 @@ void HeathrowIC::ack_int(uint32_t irq_id, uint8_t irq_line_state)
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this->int_levels1 &= ~irq_id;
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}
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}
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// signal CPU interrupt
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if (this->int_events1 || this->int_events2) {
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if (!this->cpu_int_latch) {
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this->cpu_int_latch = true;
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ppc_assert_int();
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LOG_F(5, "Heathrow: CPU INT asserted, source: %d", irq_id);
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} else {
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LOG_F(5, "Heathrow: CPU INT already latched");
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}
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}
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this->signal_cpu_int();
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} else {
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ABORT_F("Heathrow: native interrupt mode not implemented");
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ABORT_F("%s: native interrupt mode not implemented", this->name.c_str());
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}
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}
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void HeathrowIC::ack_dma_int(uint32_t irq_id, uint8_t irq_line_state)
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{
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if (this->int_mask1 & MACIO_INT_MODE) { // 68k interrupt emulation mode?
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this->int_events1 |= irq_id; // signal IRQ line change
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this->int_events1 &= this->int_mask1;
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// update IRQ line state
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if (irq_line_state) {
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this->int_levels1 |= irq_id;
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} else {
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this->int_levels1 &= ~irq_id;
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}
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this->signal_cpu_int();
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} else {
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ABORT_F("%s: native interrupt mode not implemented", this->name.c_str());
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}
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}
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void HeathrowIC::signal_cpu_int() {
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if (this->int_events1 || this->int_events2) {
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if (!this->cpu_int_latch) {
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this->cpu_int_latch = true;
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ppc_assert_int();
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} else {
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LOG_F(5, "%s: CPU INT already latched", this->name.c_str());
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}
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}
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}
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void HeathrowIC::clear_cpu_int()
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@ -247,6 +247,7 @@ protected:
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void notify_bar_change(int bar_num);
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void feature_control(const uint32_t value);
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void signal_cpu_int();
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void clear_cpu_int();
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private:
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