mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-06-25 08:29:36 +00:00
Floating-point refactor, part 3
Condensed code to shorten enum names and remove casting. Condensed mffs and partially fixed NAN checks for FADD(S).
This commit is contained in:
dingusdev
parent
2d65ed47fc
commit
5672a154cb
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@ -200,57 +200,57 @@ enum class BB_end_kind {
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BB_RFI /* the rfi instruction is encountered */
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};
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enum class CR_select {
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enum CR_select : int32_t {
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CR0_field = (0xF << 28),
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CR1_field = (0xF << 24),
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};
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enum class CRx_bit {
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enum CRx_bit : uint32_t {
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CR_SO = 0,
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CR_EQ,
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CR_GT,
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CR_LT
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};
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enum class CR1_bit {
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enum CR1_bit : uint32_t {
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CR1_OX = 24,
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CR1_VX,
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CR1_FEX,
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CR1_FX,
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};
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enum class FPSCR_bit {
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FPSCR_RN = 0x3,
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FPSCR_NI = 0x4,
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FPSCR_XE = 0x8,
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FPSCR_ZE = 0x10,
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FPSCR_UE = 0x20,
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FPSCR_OE = 0x40,
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FPSCR_VE = 0x80,
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FPSCR_VXCVI = 0x100,
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FPSCR_VXSQRT = 0x200,
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FPSCR_VXSOFT = 0x400,
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FPSCR_FPRF = 0x1F000,
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FPSCR_FPCC_FUNAN = 0x10000,
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FPSCR_FPCC_ZERO = 0x8000,
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FPSCR_FPCC_POS = 0x4000,
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FPSCR_FPCC_NEG = 0x2000,
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FPSCR_FPCC_FPRCD = 0x1000,
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FPSCR_FI = (1 << 17),
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FPSCR_FR = (1 << 18),
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FPSCR_VXVC = (1 << 19),
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FPSCR_VXIMZ = (1 << 20),
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FPSCR_VXZDZ = (1 << 21),
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FPSCR_VXIDI = (1 << 22),
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FPSCR_VXISI = (1 << 23),
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FPSCR_VXSNAN = (1 << 24),
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FPSCR_XX = (1 << 25),
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FPSCR_ZX = (1 << 26),
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FPSCR_UX = (1 << 27),
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FPSCR_OX = (1 << 28),
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FPSCR_VX = (1 << 29),
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FPSCR_FEX = (1 << 30),
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FPSCR_FX = (1 << 31)
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enum FPSCR : uint32_t {
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RN = 0x3,
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NI = 0x4,
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XE = 0x8,
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ZE = 0x10,
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UE = 0x20,
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OE = 0x40,
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VE = 0x80,
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VXCVI = 0x100,
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VXSQRT = 0x200,
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VXSOFT = 0x400,
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FPRF = 0x1F000,
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FPCC_FUNAN = 0x10000,
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FPCC_ZERO = 0x8000,
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FPCC_POS = 0x4000,
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FPCC_NEG = 0x2000,
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FPCC_FPRCD = 0x1000,
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FI = 0x20000,
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FR = 0x40000,
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VXVC = 0x80000,
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VXIMZ = 0x100000,
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VXZDZ = 0x200000,
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VXIDI = 0x400000,
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VXISI = 0x800000,
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VXSNAN = 0x1000000,
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XX = 0x2000000,
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ZX = 0x4000000,
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UX = 0x8000000,
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OX = 0x10000000,
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VX = 0x20000000,
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FEX = 0x40000000,
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FX = 0x80000000
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};
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//for inf and nan checks
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@ -180,7 +180,7 @@ int64_t round_to_neg_inf(double f) {
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return static_cast<int32_t>(floor(f));
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}
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void update_fpscr_fex() {
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void update_fex() {
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int fex_result = !!((ppc_state.fpscr & (ppc_state.fpscr << 22)) & 0x3E000000);
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ppc_state.fpscr = (ppc_state.fpscr & ~0x40000000) | (fex_result << 30);
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}
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@ -198,64 +198,64 @@ constexpr auto ppc_confirm_inf_nan(int chosen_reg_1, int chosen_reg_2, int chose
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switch (op) {
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case FPOP::DIV:
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if (isnan(input_a) && isnan(input_b)) {
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ppc_state.fpscr |= ((uint32_t)FPSCR_bit::FPSCR_FX | (uint32_t)FPSCR_bit::FPSCR_VXIDI);
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ppc_state.fpscr |= (FPSCR::FX | FPSCR::VXIDI);
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inf_or_nan = true;
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} else if ((input_a == FP_ZERO) && (input_b == FP_ZERO)) {
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ppc_state.fpscr |= ((uint32_t)FPSCR_bit::FPSCR_FX | (uint32_t)FPSCR_bit::FPSCR_VXZDZ);
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ppc_state.fpscr |= (FPSCR::FX | FPSCR::VXZDZ);
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inf_or_nan = true;
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}
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update_fpscr_fex();
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update_fex();
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return inf_or_nan;
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break;
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case FPOP::SUB:
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if (isnan(input_a) && isnan(input_b)) {
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ppc_state.fpscr |= ((uint32_t)FPSCR_bit::FPSCR_FX | (uint32_t)FPSCR_bit::FPSCR_VXISI);
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ppc_state.fpscr |= (FPSCR::FX | FPSCR::VXISI);
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inf_or_nan = true;
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}
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update_fpscr_fex();
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update_fex();
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return inf_or_nan;
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break;
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case FPOP::ADD:
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if ((isnan(input_a) & (input_b == FP_ZERO)) | (isnan(input_b) & (input_a == FP_ZERO))) {
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ppc_state.fpscr |= 0x80100000;
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if (isnan(input_a) && isnan(input_b)) {
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ppc_state.fpscr |= (FPSCR::FX | FPSCR::VXISI);
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inf_or_nan = true;
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}
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update_fpscr_fex();
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update_fex();
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return inf_or_nan;
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break;
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case FPOP::MUL:
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if (((input_a == FP_ZERO) && (input_c == FP_INFINITE)) ||
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((input_c == FP_ZERO) && (input_a == FP_INFINITE))) {
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ppc_state.fpscr |=
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((uint32_t)FPSCR_bit::FPSCR_FX | (uint32_t)FPSCR_bit::FPSCR_VXSNAN |
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(uint32_t)FPSCR_bit::FPSCR_VXIMZ);
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(FPSCR::FX | FPSCR::VXSNAN |
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FPSCR::VXIMZ);
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inf_or_nan = true;
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}
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update_fpscr_fex();
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update_fex();
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return inf_or_nan;
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break;
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case FPOP::FMSUB:
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case FPOP::FNMSUB:
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if (isnan(input_a) || isnan(input_b) || isnan(input_c)) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN;
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ppc_state.fpscr |= FPSCR::VXSNAN;
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inf_or_nan = true;
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if (((input_a == FP_ZERO) && (input_c == FP_INFINITE)) ||
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((input_c == FP_ZERO) && (input_a == FP_INFINITE))) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXIMZ;
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ppc_state.fpscr |= FPSCR::VXIMZ;
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}
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}
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update_fpscr_fex();
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update_fex();
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return inf_or_nan;
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break;
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case FPOP::FMADD:
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case FPOP::FNMADD:
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if (isnan(input_a) || isnan(input_b) || isnan(input_c)) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN;
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ppc_state.fpscr |= FPSCR::VXSNAN;
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inf_or_nan = true;
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}
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update_fpscr_fex();
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update_fex();
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return inf_or_nan;
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break;
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default:
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@ -267,23 +267,23 @@ void fpresult_update(double set_result, bool confirm_arc) {
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bool confirm_ov = (bool)std::fetestexcept(FE_OVERFLOW);
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if (confirm_ov) {
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ppc_state.fpscr |= ((uint32_t)FPSCR_bit::FPSCR_FX | ((uint32_t)FPSCR_bit::FPSCR_FPRF & (uint32_t)FPSCR_bit::FPSCR_FPCC_FUNAN));
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ppc_state.fpscr |= (FPSCR::FX | (FPSCR::FPRF & FPSCR::FPCC_FUNAN));
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}
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if (confirm_arc) {
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ppc_state.fpscr |= ((uint32_t)FPSCR_bit::FPSCR_FX | ((uint32_t)FPSCR_bit::FPSCR_FPRF & (uint32_t)FPSCR_bit::FPSCR_FPCC_FUNAN));
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ppc_state.fpscr |= (FPSCR::FX | (FPSCR::FPRF & FPSCR::FPCC_FUNAN));
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ppc_state.fpscr &= 0xFFFF0FFF;
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if (set_result == 0.0) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_FPCC_NEG;
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ppc_state.fpscr |= FPSCR::FPCC_NEG;
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} else {
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if (set_result < 0.0) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_FPCC_ZERO;
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ppc_state.fpscr |= FPSCR::FPCC_ZERO;
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} else if (set_result > 0.0) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_FPCC_POS;
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ppc_state.fpscr |= FPSCR::FPCC_POS;
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} else {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_FPCC_FPRCD;
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ppc_state.fpscr |= FPSCR::FPCC_FPRCD;
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}
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}
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}
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@ -453,8 +453,6 @@ void dppc_interpreter::ppc_fdivs() {
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void dppc_interpreter::ppc_fmadds() {
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ppc_grab_regsfpdabc();
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float intermediate;
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if (!ppc_confirm_inf_nan<float>(reg_a, reg_b, reg_c, FPOP::FMADD)) {
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ppc_dblresult64_d = static_cast<double>(std::fma(
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(float)val_reg_a, (float)val_reg_c, (float)val_reg_b));
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@ -620,13 +618,13 @@ void dppc_interpreter::ppc_fres() {
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ppc_store_dfpresult_flt(reg_d);
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if (start_num == 0.0) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_ZX;
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ppc_state.fpscr |= FPSCR::ZX;
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}
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else if (std::isnan(start_num)) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN;
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ppc_state.fpscr |= FPSCR::VXSNAN;
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}
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else if (std::isinf(start_num)){
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN;
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ppc_state.fpscr |= FPSCR::VXSNAN;
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ppc_state.fpscr &= 0xFFF9FFFF;
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}
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@ -640,15 +638,15 @@ void dppc_interpreter::ppc_fctiw() {
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if (std::isnan(val_reg_b)) {
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ppc_state.fpr[reg_d].int64_r = 0x80000000;
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN | (uint32_t)FPSCR_bit::FPSCR_VXCVI;
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ppc_state.fpscr |= FPSCR::VXSNAN | FPSCR::VXCVI;
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}
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else if (val_reg_b > static_cast<double>(0x7fffffff)) {
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ppc_state.fpr[reg_d].int64_r = 0x7fffffff;
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXCVI;
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ppc_state.fpscr |= FPSCR::VXCVI;
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}
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else if (val_reg_b < -static_cast<double>(0x80000000)) {
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ppc_state.fpr[reg_d].int64_r = 0x80000000;
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXCVI;
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ppc_state.fpscr |= FPSCR::VXCVI;
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}
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else {
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switch (ppc_state.fpscr & 0x3) {
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@ -680,15 +678,15 @@ void dppc_interpreter::ppc_fctiwz() {
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if (std::isnan(val_reg_b)) {
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ppc_state.fpr[reg_d].int64_r = 0x80000000;
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN | (uint32_t)FPSCR_bit::FPSCR_VXCVI;
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ppc_state.fpscr |= FPSCR::VXSNAN | FPSCR::VXCVI;
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}
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else if (val_reg_b > static_cast<double>(0x7fffffff)) {
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ppc_state.fpr[reg_d].int64_r = 0x7fffffff;
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXCVI;
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ppc_state.fpscr |= FPSCR::VXCVI;
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}
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else if (val_reg_b < -static_cast<double>(0x80000000)) {
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ppc_state.fpr[reg_d].int64_r = 0x80000000;
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXCVI;
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ppc_state.fpscr |= FPSCR::VXCVI;
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}
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else {
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ppc_result64_d = round_to_zero(val_reg_b);
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@ -887,17 +885,8 @@ void dppc_interpreter::ppc_fmr() {
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void dppc_interpreter::ppc_mffs() {
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ppc_grab_regsda();
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uint64_t fpstore1 = 0;
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if (ppc_state.spr[SPR::PVR] == PPC_VER::MPC601) {
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fpstore1 = ppc_state.fpr[reg_d].int64_r & ((uint64_t)0xFFF80000 << 32);
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}
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else {
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fpstore1 = ppc_state.fpr[reg_d].int64_r & ((uint64_t)0xFFFFFFFF << 32);
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}
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uint64_t fpstore2 = ppc_state.fpscr & (uint64_t)0xFFFFFFFF;
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fpstore1 |= fpstore2;
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uint64_t fpstore1 = ppc_state.fpr[reg_d].int64_r & ((uint64_t)0xFFF80000 << 32);
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fpstore1 |= (uint64_t)ppc_state.fpscr;
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fp_save_uint64(fpstore1);
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if (rc_flag)
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@ -981,17 +970,17 @@ void dppc_interpreter::ppc_fcmpo() {
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fpresult_update(db_test_a, true);
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ppc_state.fpscr = (ppc_state.fpscr & ~((uint32_t)FPSCR_bit::FPSCR_FPRF)) | (cmp_c << 12);
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ppc_state.fpscr = (ppc_state.fpscr & ~(FPSCR::FPRF)) | (cmp_c << 12);
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ppc_state.cr =
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((ppc_state.cr & ~((uint32_t)CR_select::CR0_field >> crf_d)) | ((cmp_c + xercon) >> crf_d));
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if (std::isnan(db_test_a) || std::isnan(db_test_b)) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN;
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ppc_state.fpscr |= FPSCR::VXSNAN;
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if (ppc_state.fpscr & 0x80) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXVC;
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ppc_state.fpscr |= FPSCR::VXVC;
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}
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} else if ((db_test_a == qnan) || (db_test_b == qnan)) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXVC;
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ppc_state.fpscr |= FPSCR::VXVC;
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}
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}
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@ -1012,11 +1001,11 @@ void dppc_interpreter::ppc_fcmpu() {
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fpresult_update(db_test_a, true);
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ppc_state.fpscr = (ppc_state.fpscr & ~((uint32_t)FPSCR_bit::FPSCR_FPRF)) | (cmp_c << 12);
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ppc_state.fpscr = (ppc_state.fpscr & ~(FPSCR::FPRF)) | (cmp_c << 12);
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ppc_state.cr =
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((ppc_state.cr & ~((uint32_t)CR_select::CR0_field >> crf_d)) | ((cmp_c + xercon) >> crf_d));
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if (std::isnan(db_test_a) || std::isnan(db_test_b)) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN;
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ppc_state.fpscr |= FPSCR::VXSNAN;
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}
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}
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