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Floating-point refactor, part 3

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Condensed code to shorten enum names and remove casting.

Condensed mffs and partially fixed NAN checks for FADD(S).
This commit is contained in:
dingusdev 2021-10-10 07:48:49 -07:00
parent 2d65ed47fc
commit 5672a154cb
2 changed files with 75 additions and 86 deletions
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70
cpu/ppc/ppcemu.h
View File

@ -200,57 +200,57 @@ enum class BB_end_kind {
BB_RFI /* the rfi instruction is encountered */ BB_RFI /* the rfi instruction is encountered */
}; };
enum class CR_select { enum CR_select : int32_t {
CR0_field = (0xF << 28), CR0_field = (0xF << 28),
CR1_field = (0xF << 24), CR1_field = (0xF << 24),
}; };
enum class CRx_bit { enum CRx_bit : uint32_t {
CR_SO = 0, CR_SO = 0,
CR_EQ, CR_EQ,
CR_GT, CR_GT,
CR_LT CR_LT
}; };
enum class CR1_bit { enum CR1_bit : uint32_t {
CR1_OX = 24, CR1_OX = 24,
CR1_VX, CR1_VX,
CR1_FEX, CR1_FEX,
CR1_FX, CR1_FX,
}; };
enum class FPSCR_bit { enum FPSCR : uint32_t {
FPSCR_RN = 0x3, RN = 0x3,
FPSCR_NI = 0x4, NI = 0x4,
FPSCR_XE = 0x8, XE = 0x8,
FPSCR_ZE = 0x10, ZE = 0x10,
FPSCR_UE = 0x20, UE = 0x20,
FPSCR_OE = 0x40, OE = 0x40,
FPSCR_VE = 0x80, VE = 0x80,
FPSCR_VXCVI = 0x100, VXCVI = 0x100,
FPSCR_VXSQRT = 0x200, VXSQRT = 0x200,
FPSCR_VXSOFT = 0x400, VXSOFT = 0x400,
FPSCR_FPRF = 0x1F000, FPRF = 0x1F000,
FPSCR_FPCC_FUNAN = 0x10000, FPCC_FUNAN = 0x10000,
FPSCR_FPCC_ZERO = 0x8000, FPCC_ZERO = 0x8000,
FPSCR_FPCC_POS = 0x4000, FPCC_POS = 0x4000,
FPSCR_FPCC_NEG = 0x2000, FPCC_NEG = 0x2000,
FPSCR_FPCC_FPRCD = 0x1000, FPCC_FPRCD = 0x1000,
FPSCR_FI = (1 << 17), FI = 0x20000,
FPSCR_FR = (1 << 18), FR = 0x40000,
FPSCR_VXVC = (1 << 19), VXVC = 0x80000,
FPSCR_VXIMZ = (1 << 20), VXIMZ = 0x100000,
FPSCR_VXZDZ = (1 << 21), VXZDZ = 0x200000,
FPSCR_VXIDI = (1 << 22), VXIDI = 0x400000,
FPSCR_VXISI = (1 << 23), VXISI = 0x800000,
FPSCR_VXSNAN = (1 << 24), VXSNAN = 0x1000000,
FPSCR_XX = (1 << 25), XX = 0x2000000,
FPSCR_ZX = (1 << 26), ZX = 0x4000000,
FPSCR_UX = (1 << 27), UX = 0x8000000,
FPSCR_OX = (1 << 28), OX = 0x10000000,
FPSCR_VX = (1 << 29), VX = 0x20000000,
FPSCR_FEX = (1 << 30), FEX = 0x40000000,
FPSCR_FX = (1 << 31) FX = 0x80000000
}; };
//for inf and nan checks //for inf and nan checks

91
cpu/ppc/ppcfpopcodes.cpp
View File

@ -180,7 +180,7 @@ int64_t round_to_neg_inf(double f) {
return static_cast<int32_t>(floor(f)); return static_cast<int32_t>(floor(f));
} }
void update_fpscr_fex() { void update_fex() {
int fex_result = !!((ppc_state.fpscr & (ppc_state.fpscr << 22)) & 0x3E000000); int fex_result = !!((ppc_state.fpscr & (ppc_state.fpscr << 22)) & 0x3E000000);
ppc_state.fpscr = (ppc_state.fpscr & ~0x40000000) | (fex_result << 30); ppc_state.fpscr = (ppc_state.fpscr & ~0x40000000) | (fex_result << 30);
} }
@ -198,64 +198,64 @@ constexpr auto ppc_confirm_inf_nan(int chosen_reg_1, int chosen_reg_2, int chose
switch (op) { switch (op) {
case FPOP::DIV: case FPOP::DIV:
if (isnan(input_a) && isnan(input_b)) { if (isnan(input_a) && isnan(input_b)) {
ppc_state.fpscr |= ((uint32_t)FPSCR_bit::FPSCR_FX | (uint32_t)FPSCR_bit::FPSCR_VXIDI); ppc_state.fpscr |= (FPSCR::FX | FPSCR::VXIDI);
inf_or_nan = true; inf_or_nan = true;
} else if ((input_a == FP_ZERO) && (input_b == FP_ZERO)) { } else if ((input_a == FP_ZERO) && (input_b == FP_ZERO)) {
ppc_state.fpscr |= ((uint32_t)FPSCR_bit::FPSCR_FX | (uint32_t)FPSCR_bit::FPSCR_VXZDZ); ppc_state.fpscr |= (FPSCR::FX | FPSCR::VXZDZ);
inf_or_nan = true; inf_or_nan = true;
} }
update_fpscr_fex(); update_fex();
return inf_or_nan; return inf_or_nan;
break; break;
case FPOP::SUB: case FPOP::SUB:
if (isnan(input_a) && isnan(input_b)) { if (isnan(input_a) && isnan(input_b)) {
ppc_state.fpscr |= ((uint32_t)FPSCR_bit::FPSCR_FX | (uint32_t)FPSCR_bit::FPSCR_VXISI); ppc_state.fpscr |= (FPSCR::FX | FPSCR::VXISI);
inf_or_nan = true; inf_or_nan = true;
} }
update_fpscr_fex(); update_fex();
return inf_or_nan; return inf_or_nan;
break; break;
case FPOP::ADD: case FPOP::ADD:
if ((isnan(input_a) & (input_b == FP_ZERO)) | (isnan(input_b) & (input_a == FP_ZERO))) { if (isnan(input_a) && isnan(input_b)) {
ppc_state.fpscr |= 0x80100000; ppc_state.fpscr |= (FPSCR::FX | FPSCR::VXISI);
inf_or_nan = true; inf_or_nan = true;
} }
update_fpscr_fex(); update_fex();
return inf_or_nan; return inf_or_nan;
break; break;
case FPOP::MUL: case FPOP::MUL:
if (((input_a == FP_ZERO) && (input_c == FP_INFINITE)) || if (((input_a == FP_ZERO) && (input_c == FP_INFINITE)) ||
((input_c == FP_ZERO) && (input_a == FP_INFINITE))) { ((input_c == FP_ZERO) && (input_a == FP_INFINITE))) {
ppc_state.fpscr |= ppc_state.fpscr |=
((uint32_t)FPSCR_bit::FPSCR_FX | (uint32_t)FPSCR_bit::FPSCR_VXSNAN | (FPSCR::FX | FPSCR::VXSNAN |
(uint32_t)FPSCR_bit::FPSCR_VXIMZ); FPSCR::VXIMZ);
inf_or_nan = true; inf_or_nan = true;
} }
update_fpscr_fex(); update_fex();
return inf_or_nan; return inf_or_nan;
break; break;
case FPOP::FMSUB: case FPOP::FMSUB:
case FPOP::FNMSUB: case FPOP::FNMSUB:
if (isnan(input_a) || isnan(input_b) || isnan(input_c)) { if (isnan(input_a) || isnan(input_b) || isnan(input_c)) {
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN; ppc_state.fpscr |= FPSCR::VXSNAN;
inf_or_nan = true; inf_or_nan = true;
if (((input_a == FP_ZERO) && (input_c == FP_INFINITE)) || if (((input_a == FP_ZERO) && (input_c == FP_INFINITE)) ||
((input_c == FP_ZERO) && (input_a == FP_INFINITE))) { ((input_c == FP_ZERO) && (input_a == FP_INFINITE))) {
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXIMZ; ppc_state.fpscr |= FPSCR::VXIMZ;
} }
} }
update_fpscr_fex(); update_fex();
return inf_or_nan; return inf_or_nan;
break; break;
case FPOP::FMADD: case FPOP::FMADD:
case FPOP::FNMADD: case FPOP::FNMADD:
if (isnan(input_a) || isnan(input_b) || isnan(input_c)) { if (isnan(input_a) || isnan(input_b) || isnan(input_c)) {
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN; ppc_state.fpscr |= FPSCR::VXSNAN;
inf_or_nan = true; inf_or_nan = true;
} }
update_fpscr_fex(); update_fex();
return inf_or_nan; return inf_or_nan;
break; break;
default: default:
@ -267,23 +267,23 @@ void fpresult_update(double set_result, bool confirm_arc) {
bool confirm_ov = (bool)std::fetestexcept(FE_OVERFLOW); bool confirm_ov = (bool)std::fetestexcept(FE_OVERFLOW);
if (confirm_ov) { if (confirm_ov) {
ppc_state.fpscr |= ((uint32_t)FPSCR_bit::FPSCR_FX | ((uint32_t)FPSCR_bit::FPSCR_FPRF & (uint32_t)FPSCR_bit::FPSCR_FPCC_FUNAN)); ppc_state.fpscr |= (FPSCR::FX | (FPSCR::FPRF & FPSCR::FPCC_FUNAN));
} }
if (confirm_arc) { if (confirm_arc) {
ppc_state.fpscr |= ((uint32_t)FPSCR_bit::FPSCR_FX | ((uint32_t)FPSCR_bit::FPSCR_FPRF & (uint32_t)FPSCR_bit::FPSCR_FPCC_FUNAN)); ppc_state.fpscr |= (FPSCR::FX | (FPSCR::FPRF & FPSCR::FPCC_FUNAN));
ppc_state.fpscr &= 0xFFFF0FFF; ppc_state.fpscr &= 0xFFFF0FFF;
if (set_result == 0.0) { if (set_result == 0.0) {
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_FPCC_NEG; ppc_state.fpscr |= FPSCR::FPCC_NEG;
} else { } else {
if (set_result < 0.0) { if (set_result < 0.0) {
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_FPCC_ZERO; ppc_state.fpscr |= FPSCR::FPCC_ZERO;
} else if (set_result > 0.0) { } else if (set_result > 0.0) {
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_FPCC_POS; ppc_state.fpscr |= FPSCR::FPCC_POS;
} else { } else {
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_FPCC_FPRCD; ppc_state.fpscr |= FPSCR::FPCC_FPRCD;
} }
} }
} }
@ -453,8 +453,6 @@ void dppc_interpreter::ppc_fdivs() {
void dppc_interpreter::ppc_fmadds() { void dppc_interpreter::ppc_fmadds() {
ppc_grab_regsfpdabc(); ppc_grab_regsfpdabc();
float intermediate;
if (!ppc_confirm_inf_nan<float>(reg_a, reg_b, reg_c, FPOP::FMADD)) { if (!ppc_confirm_inf_nan<float>(reg_a, reg_b, reg_c, FPOP::FMADD)) {
ppc_dblresult64_d = static_cast<double>(std::fma( ppc_dblresult64_d = static_cast<double>(std::fma(
(float)val_reg_a, (float)val_reg_c, (float)val_reg_b)); (float)val_reg_a, (float)val_reg_c, (float)val_reg_b));
@ -620,13 +618,13 @@ void dppc_interpreter::ppc_fres() {
ppc_store_dfpresult_flt(reg_d); ppc_store_dfpresult_flt(reg_d);
if (start_num == 0.0) { if (start_num == 0.0) {
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_ZX; ppc_state.fpscr |= FPSCR::ZX;
} }
else if (std::isnan(start_num)) { else if (std::isnan(start_num)) {
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN; ppc_state.fpscr |= FPSCR::VXSNAN;
} }
else if (std::isinf(start_num)){ else if (std::isinf(start_num)){
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN; ppc_state.fpscr |= FPSCR::VXSNAN;
ppc_state.fpscr &= 0xFFF9FFFF; ppc_state.fpscr &= 0xFFF9FFFF;
} }
@ -640,15 +638,15 @@ void dppc_interpreter::ppc_fctiw() {
if (std::isnan(val_reg_b)) { if (std::isnan(val_reg_b)) {
ppc_state.fpr[reg_d].int64_r = 0x80000000; ppc_state.fpr[reg_d].int64_r = 0x80000000;
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN | (uint32_t)FPSCR_bit::FPSCR_VXCVI; ppc_state.fpscr |= FPSCR::VXSNAN | FPSCR::VXCVI;
} }
else if (val_reg_b > static_cast<double>(0x7fffffff)) { else if (val_reg_b > static_cast<double>(0x7fffffff)) {
ppc_state.fpr[reg_d].int64_r = 0x7fffffff; ppc_state.fpr[reg_d].int64_r = 0x7fffffff;
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXCVI; ppc_state.fpscr |= FPSCR::VXCVI;
} }
else if (val_reg_b < -static_cast<double>(0x80000000)) { else if (val_reg_b < -static_cast<double>(0x80000000)) {
ppc_state.fpr[reg_d].int64_r = 0x80000000; ppc_state.fpr[reg_d].int64_r = 0x80000000;
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXCVI; ppc_state.fpscr |= FPSCR::VXCVI;
} }
else { else {
switch (ppc_state.fpscr & 0x3) { switch (ppc_state.fpscr & 0x3) {
@ -680,15 +678,15 @@ void dppc_interpreter::ppc_fctiwz() {
if (std::isnan(val_reg_b)) { if (std::isnan(val_reg_b)) {
ppc_state.fpr[reg_d].int64_r = 0x80000000; ppc_state.fpr[reg_d].int64_r = 0x80000000;
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN | (uint32_t)FPSCR_bit::FPSCR_VXCVI; ppc_state.fpscr |= FPSCR::VXSNAN | FPSCR::VXCVI;
} }
else if (val_reg_b > static_cast<double>(0x7fffffff)) { else if (val_reg_b > static_cast<double>(0x7fffffff)) {
ppc_state.fpr[reg_d].int64_r = 0x7fffffff; ppc_state.fpr[reg_d].int64_r = 0x7fffffff;
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXCVI; ppc_state.fpscr |= FPSCR::VXCVI;
} }
else if (val_reg_b < -static_cast<double>(0x80000000)) { else if (val_reg_b < -static_cast<double>(0x80000000)) {
ppc_state.fpr[reg_d].int64_r = 0x80000000; ppc_state.fpr[reg_d].int64_r = 0x80000000;
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXCVI; ppc_state.fpscr |= FPSCR::VXCVI;
} }
else { else {
ppc_result64_d = round_to_zero(val_reg_b); ppc_result64_d = round_to_zero(val_reg_b);
@ -887,17 +885,8 @@ void dppc_interpreter::ppc_fmr() {
void dppc_interpreter::ppc_mffs() { void dppc_interpreter::ppc_mffs() {
ppc_grab_regsda(); ppc_grab_regsda();
uint64_t fpstore1 = 0; uint64_t fpstore1 = ppc_state.fpr[reg_d].int64_r & ((uint64_t)0xFFF80000 << 32);
fpstore1 |= (uint64_t)ppc_state.fpscr;
if (ppc_state.spr[SPR::PVR] == PPC_VER::MPC601) {
fpstore1 = ppc_state.fpr[reg_d].int64_r & ((uint64_t)0xFFF80000 << 32);
}
else {
fpstore1 = ppc_state.fpr[reg_d].int64_r & ((uint64_t)0xFFFFFFFF << 32);
}
uint64_t fpstore2 = ppc_state.fpscr & (uint64_t)0xFFFFFFFF;
fpstore1 |= fpstore2;
fp_save_uint64(fpstore1); fp_save_uint64(fpstore1);
if (rc_flag) if (rc_flag)
@ -981,17 +970,17 @@ void dppc_interpreter::ppc_fcmpo() {
fpresult_update(db_test_a, true); fpresult_update(db_test_a, true);
ppc_state.fpscr = (ppc_state.fpscr & ~((uint32_t)FPSCR_bit::FPSCR_FPRF)) | (cmp_c << 12); ppc_state.fpscr = (ppc_state.fpscr & ~(FPSCR::FPRF)) | (cmp_c << 12);
ppc_state.cr = ppc_state.cr =
((ppc_state.cr & ~((uint32_t)CR_select::CR0_field >> crf_d)) | ((cmp_c + xercon) >> crf_d)); ((ppc_state.cr & ~((uint32_t)CR_select::CR0_field >> crf_d)) | ((cmp_c + xercon) >> crf_d));
if (std::isnan(db_test_a) || std::isnan(db_test_b)) { if (std::isnan(db_test_a) || std::isnan(db_test_b)) {
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN; ppc_state.fpscr |= FPSCR::VXSNAN;
if (ppc_state.fpscr & 0x80) { if (ppc_state.fpscr & 0x80) {
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXVC; ppc_state.fpscr |= FPSCR::VXVC;
} }
} else if ((db_test_a == qnan) || (db_test_b == qnan)) { } else if ((db_test_a == qnan) || (db_test_b == qnan)) {
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXVC; ppc_state.fpscr |= FPSCR::VXVC;
} }
} }
@ -1012,11 +1001,11 @@ void dppc_interpreter::ppc_fcmpu() {
fpresult_update(db_test_a, true); fpresult_update(db_test_a, true);
ppc_state.fpscr = (ppc_state.fpscr & ~((uint32_t)FPSCR_bit::FPSCR_FPRF)) | (cmp_c << 12); ppc_state.fpscr = (ppc_state.fpscr & ~(FPSCR::FPRF)) | (cmp_c << 12);
ppc_state.cr = ppc_state.cr =
((ppc_state.cr & ~((uint32_t)CR_select::CR0_field >> crf_d)) | ((cmp_c + xercon) >> crf_d)); ((ppc_state.cr & ~((uint32_t)CR_select::CR0_field >> crf_d)) | ((cmp_c + xercon) >> crf_d));
if (std::isnan(db_test_a) || std::isnan(db_test_b)) { if (std::isnan(db_test_a) || std::isnan(db_test_b)) {
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN; ppc_state.fpscr |= FPSCR::VXSNAN;
} }
} }