Disassembler - floating point instruction fixes

This commit is contained in:
dingusdev 2021-01-23 22:44:14 -07:00
parent 680b437b74
commit 593230f326
2 changed files with 46 additions and 11 deletions

View File

@ -1737,7 +1737,7 @@ void opc_group63(PPCDisasmContext* ctx) {
if (ra != 0) if (ra != 0)
opc_illegal(ctx); opc_illegal(ctx);
else else
ctx->instr_str = my_sprintf("%-8sr%d, r%d", opcode, rs, rb); ctx->instr_str = my_sprintf("%-8sf%d, f%d", opcode, rs, rb);
break; break;
case 64: case 64:
strcpy(opcode, "mcrfs"); strcpy(opcode, "mcrfs");
@ -1750,31 +1750,52 @@ void opc_group63(PPCDisasmContext* ctx) {
if (rc_set) if (rc_set)
strcat(opcode, "."); strcat(opcode, ".");
ctx->instr_str = my_sprintf("%-8scrb%d", opcode, rs); ctx->instr_str = my_sprintf("%-8s%d", opcode, rs);
break; break;
case 72: /* fmr */ case 72: /* fmr */
if (ra != 0) if (ra != 0)
opc_illegal(ctx); opc_illegal(ctx);
else else {
ctx->instr_str = my_sprintf("%-8sr%d, r%d", "fmr", rs, rb); strcpy(opcode, "fmr");
if (rc_set)
strcat(opcode, ".");
ctx->instr_str = my_sprintf("%-8sf%d, f%d", opcode, rs, rb);
}
break; break;
case 134: /* mtfsfi */ case 134: /* mtfsfi */
if (ra != 0) if (ra != 0)
opc_illegal(ctx); opc_illegal(ctx);
else else {
ctx->instr_str = my_sprintf("%-8scr%d, r%d", "mtfsfi", (rs >> 2), (rb >> 1)); strcpy(opcode, "mtfsfi");
if (rc_set)
strcat(opcode, ".");
ctx->instr_str = my_sprintf("%-8scr%d, %d", opcode, (rs >> 2), (rb >> 1));
}
break; break;
case 136: /* fnabs */ case 136: /* fnabs */
if (ra != 0) if (ra != 0)
opc_illegal(ctx); opc_illegal(ctx);
else else {
ctx->instr_str = my_sprintf("%-8sf%d, f%d", "fnabs", rs, rb); strcpy(opcode, "fnabs");
if (rc_set)
strcat(opcode, ".");
ctx->instr_str = my_sprintf("%-8sf%d, f%d", opcode, rs, rb);
}
break; break;
case 264: /* fabs */ case 264: /* fabs */
if (ra != 0) if (ra != 0)
opc_illegal(ctx); opc_illegal(ctx);
else else {
ctx->instr_str = my_sprintf("%-8s%d, f%d, f%d", "fabs", rs, rb); strcpy(opcode, "fabs");
if (rc_set)
strcat(opcode, ".");
ctx->instr_str = my_sprintf("%-8sf%d, f%d", opcode, rs, rb);
}
break; break;
case 583: /* mffs */ case 583: /* mffs */
strcpy(opcode, "mffs"); strcpy(opcode, "mffs");
@ -1788,7 +1809,12 @@ void opc_group63(PPCDisasmContext* ctx) {
ctx->instr_str = my_sprintf("%-8sf%d", opcode, rs); ctx->instr_str = my_sprintf("%-8sf%d", opcode, rs);
break; break;
case 711: /* mtfsf */ case 711: /* mtfsf */
ctx->instr_str = my_sprintf("%-8sfm%d, r%d", "mtfsf", fm, rb); strcpy(opcode, "mtfsf");
if (rc_set)
strcat(opcode, ".");
ctx->instr_str = my_sprintf("%-8s%d, f%d", opcode, fm, rb);
break; break;
default: default:
opc_illegal(ctx); opc_illegal(ctx);

View File

@ -362,6 +362,8 @@
0xFFF00100,0xEDA66279,fmsubs.,f13,f6,f9,f12 0xFFF00100,0xEDA66279,fmsubs.,f13,f6,f9,f12
0xFFF00100,0xEC00637C,fnmsubs,f0,f0,f13,f12 0xFFF00100,0xEC00637C,fnmsubs,f0,f0,f13,f12
0xFFF00100,0xFE0820AF,fsel.,f16,f8,f2,f4 0xFFF00100,0xFE0820AF,fsel.,f16,f8,f2,f4
0xFFF00100,0xFDA06050,fneg,f13,f12
0xFFF00100,0xFD80EA10,fabs,f12,f29
0xFFF00100,0xFD600110,fnabs,f11,f0 0xFFF00100,0xFD600110,fnabs,f11,f0
0xFFF00100,0xFD002034,frsqrte,f8,f4 0xFFF00100,0xFD002034,frsqrte,f8,f4
0xFFF00100,0x7FF957AE,stfiwx,f31,r25,r10 0xFFF00100,0x7FF957AE,stfiwx,f31,r25,r10
@ -369,6 +371,12 @@
0xFFF00100,0xFC201019,frsp.,f1,f2 0xFFF00100,0xFC201019,frsp.,f1,f2
0xFFF00100,0xFDA0F81E,fctiwz,f13,f31 0xFFF00100,0xFDA0F81E,fctiwz,f13,f31
0xFFF00100,0xFCA0501D,fctiw.,f5,f10 0xFFF00100,0xFCA0501D,fctiw.,f5,f10
0xFFF00100,0xFD9C0080,mcrfs,cr3,cr7
0xFFF00100,0xFDFE058E,mtfsf,255,f0
0xFFF00100,0xFF80F10C,mtfsfi,cr7,15
0xFFF00100,0xFF80F10D,mtfsfi.,cr7,15
0xFFF00100,0xFC406890,fmr,f2,f13
0xFFF00100,0xFC20E891,fmr.,f1,f29
# compare instructions # compare instructions
0xFFF00100,0x7C15A000,cmpw,r21,r20 0xFFF00100,0x7C15A000,cmpw,r21,r20
@ -388,6 +396,7 @@
0xFFF00100,0x7CBC04AA,lswi,r5,r28,0x20 0xFFF00100,0x7CBC04AA,lswi,r5,r28,0x20
0xFFF00100,0x7FEF2C2A,lswx,r31,r15,r5 0xFFF00100,0x7FEF2C2A,lswx,r31,r15,r5
0xFFF00100,0x7E000400,mcrxr,cr4 0xFFF00100,0x7E000400,mcrxr,cr4
0xFFF00100,0xFDC0008C,mtfsb0,14
0xFFF00100,0xFFE0004C,mtfsb1,31 0xFFF00100,0xFFE0004C,mtfsb1,31
0xFFF00100,0xFFE0048F,mffs.,f31 0xFFF00100,0xFFE0048F,mffs.,f31
0xFFF00100,0x7C2000A6,mfmsr,r1 0xFFF00100,0x7C2000A6,mfmsr,r1

1 # Test data for PowerPC disassembler supplied as comma-separated values
362 0xFFF00100,0x7D290034,cntlzw,r9,r9 0xFFF00100,0x7FBFB800,cmp,cr7,r31,r23
363 0xFFF00100,0x7FFF0035,cntlzw.,r31,r31 0xFFF00100,0x7C053040,cmplw,r5,r6
364 0xFFF00100,0x7C00D7AC,icbi,0,r26 0xFFF00100,0x7F804840,cmplw,cr7,r0,r9
365 0xFFF00100,0x2F800000,cmpwi,cr7,r0,0x0
366 0xFFF00100,0x298E0022,cmplwi,cr3,r14,0x22
367 0xFFF00100,0x7D604828,lwarx,r11,0,r9 0xFFF00100,0xFE17C840,fcmpo,cr4,f23,f25
368 0xFFF00100,0x7CBC04AA,lswi,r5,r28,0x20 0xFFF00100,0xFF0C6800,fcmpu,cr6,f12,f13
369 0xFFF00100,0x7FEF2C2A,lswx,r31,r15,r5 # misc instructions
371 0xFFF00100,0xFFE0004C,mtfsb1,31 0xFFF00100,0x7FFF0035,cntlzw.,r31,r31
372 0xFFF00100,0xFFE0048F,mffs.,f31 0xFFF00100,0x7C00D7AC,icbi,0,r26
373 0xFFF00100,0x7C2000A6,mfmsr,r1 0xFFF00100,0x7D604828,lwarx,r11,0,r9
374 0xFFF00100,0x7CBC04AA,lswi,r5,r28,0x20
375 0xFFF00100,0x7FEF2C2A,lswx,r31,r15,r5
376 0xFFF00100,0x7E000400,mcrxr,cr4
377 0xFFF00100,0xFDC0008C,mtfsb0,14
378 0xFFF00100,0xFFE0004C,mtfsb1,31
379 0xFFF00100,0xFFE0048F,mffs.,f31
380 0xFFF00100,0x7C000124,mtmsr,r0 0xFFF00100,0x7C2000A6,mfmsr,r1
381 0xFFF00100,0x7FEF01A4,mtsr,15,r31 0xFFF00100,0x7C000124,mtmsr,r0
382 0xFFF00100,0x7C6021E4,mtsrin,r3,r4 0xFFF00100,0x7FEF01A4,mtsr,15,r31
396 0xFFF00100,0x7F800009,dc.l,0x7F800009 0xFFF00100,0x7D49F02F,dc.l,0x7D49F02F
397 0xFFF00100,0x7C6B0CD0,dc.l,0x7C6B0CD0 0xFFF00100,0x7F800009,dc.l,0x7F800009
398 0xFFF00100,0x7C642D90,dc.l,0x7C642D90 0xFFF00100,0x7C6B0CD0,dc.l,0x7C6B0CD0
399 0xFFF00100,0x7C642D90,dc.l,0x7C642D90
400 # POWER/PPC601 specific instructions
401 0xFFF00100,0x7C440426,clcs,r2,r4
402 0xFFF00100,0x24000800,dozi,r0,r0,0x800