From 67a5c39b1c7de3b50f18a6b69d1b8bee40d6e55c Mon Sep 17 00:00:00 2001
From: joevt <joevt@shaw.ca>
Date: Mon, 8 Apr 2024 22:35:37 -0700
Subject: [PATCH] ppcopcodes: Add Privileged exception for SPRs.

Accessing an SPR with bit 4 set (> 15) requires supervisor privilege and should cause a supervisor-level instruction exception (privileged instruction type program exception).
---
 cpu/ppc/ppcopcodes.cpp | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/cpu/ppc/ppcopcodes.cpp b/cpu/ppc/ppcopcodes.cpp
index 41198ad..2830c07 100644
--- a/cpu/ppc/ppcopcodes.cpp
+++ b/cpu/ppc/ppcopcodes.cpp
@@ -888,11 +888,14 @@ void dppc_interpreter::ppc_mfspr() {
     ppc_grab_dab(ppc_cur_instruction);
     uint32_t ref_spr = (reg_b << 5) | reg_a;
 
+    if (ref_spr & 0x10) {
 #ifdef CPU_PROFILING
-    if (ref_spr > 31) {
         num_supervisor_instrs++;
-    }
 #endif
+        if (ppc_state.msr & MSR::PR) {
+            ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::NOT_ALLOWED);
+        }
+    }
 
     switch (ref_spr) {
     case SPR::RTCL_U:
@@ -915,11 +918,14 @@ void dppc_interpreter::ppc_mtspr() {
     ppc_grab_dab(ppc_cur_instruction);
     uint32_t ref_spr = (reg_b << 5) | reg_a;
 
+    if (ref_spr & 0x10) {
 #ifdef CPU_PROFILING
-    if (ref_spr > 31) {
         num_supervisor_instrs++;
-    }
 #endif
+        if (ppc_state.msr & MSR::PR) {
+            ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::NOT_ALLOWED);
+        }
+    }
 
     if (ref_spr == SPR::PVR || (
         ref_spr == SPR::MQ && !is_601