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https://github.com/dingusdev/dingusppc.git
synced 2024-12-23 06:29:38 +00:00
Fixed disassembly for fctiwz, frsp, and fctiw
This commit is contained in:
dingusdev
parent
3189876d41
commit
680b437b74
@ -16,7 +16,7 @@ if (UNIX AND NOT APPLE)
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endif()
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endif()
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option(DPPC_BUILD_PPC_TESTS "Build PowerPC tests" OFF)
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option(DPPC_BUILD_PPC_TESTS "Build PowerPC tests" ON)
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option(DPPC_BUILD_BENCHMARKS "Build benchmarking programs" OFF)
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option(ENABLE_68K_DEBUGGER "Enable 68k debugging" OFF)
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@ -347,10 +347,10 @@ void opc_ar_im(PPCDisasmContext* ctx) {
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int32_t imm = SIGNEXT(ctx->instr_code & 0xFFFF, 15);
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if (ctx->simplified) {
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if (((ctx->instr_code >> 26) == 0xE) & !ra) {
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if (((ctx->instr_code >> 26) == 0xE) && !ra) {
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fmt_twoop_simm(ctx->instr_str, "li", rd, imm);
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return;
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} else if (((ctx->instr_code >> 26) == 0xF) & !ra) {
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} else if (((ctx->instr_code >> 26) == 0xF) && !ra) {
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fmt_twoop_simm(ctx->instr_str, "lis", rd, imm);
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return;
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}
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@ -954,12 +954,12 @@ void opc_group31(PPCDisasmContext* ctx) {
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} else if (index == 11) { /* tlbia */
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ctx->instr_str = my_sprintf("%-8s", "tlbia");
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} else if (index == 30) { /* tlbld - 603 only */
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if (!rs & !ra)
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if (!rs && !ra)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8sr%s", "tlbld", rb);
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} else if (index == 30) { /* tlbli - 603 only */
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if (!rs & !ra)
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if (!rs && !ra)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8sr%s", "tlbli", rb);
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@ -973,10 +973,10 @@ void opc_group31(PPCDisasmContext* ctx) {
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strcat(opcode, ".");
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if ((index == 0) | (index == 4) | (index == 6) | (index == 16) | (index == 20) |
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(index == 22) | (index == 24) | (index == 28)) {
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if ((index == 0) || (index == 4) || (index == 6) || (index == 16) || (index == 20) ||
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(index == 22) || (index == 24) || (index == 28)) {
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fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
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} else if ((index == 5) | (index == 7) | (index == 21) | (index == 23) | (index == 25) | (index == 29)) {
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} else if ((index == 5) || (index == 7) || (index == 21) || (index == 23) || (index == 25) || (index == 29)) {
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fmt_threeop_simm(ctx->instr_str, opcode, ra, rs, rb);
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} else {
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opc_illegal(ctx);
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@ -990,7 +990,7 @@ void opc_group31(PPCDisasmContext* ctx) {
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if (rc_set)
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strcat(opcode, ".");
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if ((index == 4) | (index == 6) | (index == 16) | (index == 20) | (index == 22) |
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if ((index == 4) || (index == 6) || (index == 16) || (index == 20) || (index == 22) ||
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(index == 28)) {
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fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
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} else {
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@ -1077,7 +1077,7 @@ void opc_group31(PPCDisasmContext* ctx) {
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}
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}
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/* eciwx, ecowx, lhbrx, lwbrx, stwbrx, sthbrx */
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else if ((index == 9) | (index == 13) | (index == 16) | (index == 20) | (index == 24) | (index == 28)) {
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else if ((index == 9) || (index == 13) || (index == 16) || (index == 20) || (index == 24) || (index == 28)) {
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if (rc_set) {
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opc_illegal(ctx);
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return;
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@ -1088,15 +1088,15 @@ void opc_group31(PPCDisasmContext* ctx) {
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fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
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return;
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}
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} else if ((index == 18) | (index == 26)) { /* sync, eieio */
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} else if ((index == 18) || (index == 26)) { /* sync, eieio */
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ctx->instr_str = my_sprintf("%-8s", opcode);
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return;
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}
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/* dcba, dcbf, dcbi, dcbst, dcbt, dcbz, icbi */
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else if (
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(index == 1) | (index == 2) | (index == 7) | (index == 8) | (index == 14) |
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(index == 23) | (index == 30) | (index == 31)) {
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if (rc_set | (rs != 0)) {
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(index == 1) || (index == 2) || (index == 7) || (index == 8) || (index == 14) ||
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(index == 23) || (index == 30) || (index == 31)) {
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if (rc_set || (rs != 0)) {
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opc_illegal(ctx);
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return;
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} else {
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@ -1449,7 +1449,7 @@ void opc_group59(PPCDisasmContext* ctx) {
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if (rc_set)
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strcat(opcode, ".");
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if ((rc != 0) | (ra != 0))
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if ((rc != 0) || (ra != 0))
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opc_illegal(ctx);
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else
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fmt_twoop_flt(ctx->instr_str, "fsqrts", rs, rb);
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@ -1462,7 +1462,7 @@ void opc_group59(PPCDisasmContext* ctx) {
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if (rc_set)
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strcat(opcode, ".");
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if ((rc != 0) | (ra != 0))
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if ((rc != 0) || (ra != 0))
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opc_illegal(ctx);
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else
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fmt_twoop_flt(ctx->instr_str, opcode, rs, rb);
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@ -1590,7 +1590,7 @@ void opc_group63(PPCDisasmContext* ctx) {
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if (rc_set)
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strcat(opcode, ".");
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if ((rc != 0) | (ra != 0))
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if ((rc != 0) || (ra != 0))
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opc_illegal(ctx);
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else
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fmt_threeop_flt(ctx->instr_str, opcode, rs, ra, rb);
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@ -1627,7 +1627,7 @@ void opc_group63(PPCDisasmContext* ctx) {
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if (rc_set)
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strcat(opcode, ".");
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if ((rc != 0) | (ra != 0))
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if ((rc != 0) || (ra != 0))
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8sf%d, f%d", opcode, rs, rb);
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@ -1697,14 +1697,22 @@ void opc_group63(PPCDisasmContext* ctx) {
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case 14: /* fctiw */
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if (ra != 0)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8s%d, r%d, r%d", "fctiw", rs, rb);
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else {
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strcpy(opcode, "fctiw");
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if (rc_set)
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strcat(opcode, ".");
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ctx->instr_str = my_sprintf("%-8sf%d, f%d", opcode, rs, rb);
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}
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break;
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case 15: /* fctiwz */
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if (ra != 0)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8s%d, r%d, r%d", "fctiwz", rs, rb);
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else {
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strcpy(opcode, "fctiwz");
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if (rc_set)
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strcat(opcode, ".");
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ctx->instr_str = my_sprintf("%-8sf%d, f%d", opcode, rs, rb);
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}
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break;
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case 32: /* fcmpo */
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if (rs & 3)
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@ -1774,7 +1782,7 @@ void opc_group63(PPCDisasmContext* ctx) {
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if (rc_set)
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strcat(opcode, ".");
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if ((ra != 0) | (rb != 0))
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if ((ra != 0) || (rb != 0))
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8sf%d", opcode, rs);
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@ -367,6 +367,8 @@
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0xFFF00100,0x7FF957AE,stfiwx,f31,r25,r10
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0xFFF00100,0xFC40F818,frsp,f2,f31
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0xFFF00100,0xFC201019,frsp.,f1,f2
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0xFFF00100,0xFDA0F81E,fctiwz,f13,f31
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0xFFF00100,0xFCA0501D,fctiw.,f5,f10
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# compare instructions
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0xFFF00100,0x7C15A000,cmpw,r21,r20
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