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Fixed disassembly for fctiwz, frsp, and fctiw

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This commit is contained in:
dingusdev 2021-01-23 21:30:29 -07:00
parent 3189876d41
commit 680b437b74
3 changed files with 33 additions and 23 deletions
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2
CMakeLists.txt
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@ -16,7 +16,7 @@ if (UNIX AND NOT APPLE)
endif() endif()
endif() endif()
option(DPPC_BUILD_PPC_TESTS "Build PowerPC tests" OFF) option(DPPC_BUILD_PPC_TESTS "Build PowerPC tests" ON)
option(DPPC_BUILD_BENCHMARKS "Build benchmarking programs" OFF) option(DPPC_BUILD_BENCHMARKS "Build benchmarking programs" OFF)
option(ENABLE_68K_DEBUGGER "Enable 68k debugging" OFF) option(ENABLE_68K_DEBUGGER "Enable 68k debugging" OFF)

52
cpu/ppc/ppcdisasm.cpp
View File

@ -347,10 +347,10 @@ void opc_ar_im(PPCDisasmContext* ctx) {
int32_t imm = SIGNEXT(ctx->instr_code & 0xFFFF, 15); int32_t imm = SIGNEXT(ctx->instr_code & 0xFFFF, 15);
if (ctx->simplified) { if (ctx->simplified) {
if (((ctx->instr_code >> 26) == 0xE) & !ra) { if (((ctx->instr_code >> 26) == 0xE) && !ra) {
fmt_twoop_simm(ctx->instr_str, "li", rd, imm); fmt_twoop_simm(ctx->instr_str, "li", rd, imm);
return; return;
} else if (((ctx->instr_code >> 26) == 0xF) & !ra) { } else if (((ctx->instr_code >> 26) == 0xF) && !ra) {
fmt_twoop_simm(ctx->instr_str, "lis", rd, imm); fmt_twoop_simm(ctx->instr_str, "lis", rd, imm);
return; return;
} }
@ -954,12 +954,12 @@ void opc_group31(PPCDisasmContext* ctx) {
} else if (index == 11) { /* tlbia */ } else if (index == 11) { /* tlbia */
ctx->instr_str = my_sprintf("%-8s", "tlbia"); ctx->instr_str = my_sprintf("%-8s", "tlbia");
} else if (index == 30) { /* tlbld - 603 only */ } else if (index == 30) { /* tlbld - 603 only */
if (!rs & !ra) if (!rs && !ra)
opc_illegal(ctx); opc_illegal(ctx);
else else
ctx->instr_str = my_sprintf("%-8sr%s", "tlbld", rb); ctx->instr_str = my_sprintf("%-8sr%s", "tlbld", rb);
} else if (index == 30) { /* tlbli - 603 only */ } else if (index == 30) { /* tlbli - 603 only */
if (!rs & !ra) if (!rs && !ra)
opc_illegal(ctx); opc_illegal(ctx);
else else
ctx->instr_str = my_sprintf("%-8sr%s", "tlbli", rb); ctx->instr_str = my_sprintf("%-8sr%s", "tlbli", rb);
@ -973,10 +973,10 @@ void opc_group31(PPCDisasmContext* ctx) {
strcat(opcode, "."); strcat(opcode, ".");
if ((index == 0) | (index == 4) | (index == 6) | (index == 16) | (index == 20) | if ((index == 0) || (index == 4) || (index == 6) || (index == 16) || (index == 20) ||
(index == 22) | (index == 24) | (index == 28)) { (index == 22) || (index == 24) || (index == 28)) {
fmt_threeop(ctx->instr_str, opcode, ra, rs, rb); fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
} else if ((index == 5) | (index == 7) | (index == 21) | (index == 23) | (index == 25) | (index == 29)) { } else if ((index == 5) || (index == 7) || (index == 21) || (index == 23) || (index == 25) || (index == 29)) {
fmt_threeop_simm(ctx->instr_str, opcode, ra, rs, rb); fmt_threeop_simm(ctx->instr_str, opcode, ra, rs, rb);
} else { } else {
opc_illegal(ctx); opc_illegal(ctx);
@ -990,7 +990,7 @@ void opc_group31(PPCDisasmContext* ctx) {
if (rc_set) if (rc_set)
strcat(opcode, "."); strcat(opcode, ".");
if ((index == 4) | (index == 6) | (index == 16) | (index == 20) | (index == 22) | if ((index == 4) || (index == 6) || (index == 16) || (index == 20) || (index == 22) ||
(index == 28)) { (index == 28)) {
fmt_threeop(ctx->instr_str, opcode, ra, rs, rb); fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
} else { } else {
@ -1077,7 +1077,7 @@ void opc_group31(PPCDisasmContext* ctx) {
} }
} }
/* eciwx, ecowx, lhbrx, lwbrx, stwbrx, sthbrx */ /* eciwx, ecowx, lhbrx, lwbrx, stwbrx, sthbrx */
else if ((index == 9) | (index == 13) | (index == 16) | (index == 20) | (index == 24) | (index == 28)) { else if ((index == 9) || (index == 13) || (index == 16) || (index == 20) || (index == 24) || (index == 28)) {
if (rc_set) { if (rc_set) {
opc_illegal(ctx); opc_illegal(ctx);
return; return;
@ -1088,15 +1088,15 @@ void opc_group31(PPCDisasmContext* ctx) {
fmt_threeop(ctx->instr_str, opcode, rs, ra, rb); fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
return; return;
} }
} else if ((index == 18) | (index == 26)) { /* sync, eieio */ } else if ((index == 18) || (index == 26)) { /* sync, eieio */
ctx->instr_str = my_sprintf("%-8s", opcode); ctx->instr_str = my_sprintf("%-8s", opcode);
return; return;
} }
/* dcba, dcbf, dcbi, dcbst, dcbt, dcbz, icbi */ /* dcba, dcbf, dcbi, dcbst, dcbt, dcbz, icbi */
else if ( else if (
(index == 1) | (index == 2) | (index == 7) | (index == 8) | (index == 14) | (index == 1) || (index == 2) || (index == 7) || (index == 8) || (index == 14) ||
(index == 23) | (index == 30) | (index == 31)) { (index == 23) || (index == 30) || (index == 31)) {
if (rc_set | (rs != 0)) { if (rc_set || (rs != 0)) {
opc_illegal(ctx); opc_illegal(ctx);
return; return;
} else { } else {
@ -1449,7 +1449,7 @@ void opc_group59(PPCDisasmContext* ctx) {
if (rc_set) if (rc_set)
strcat(opcode, "."); strcat(opcode, ".");
if ((rc != 0) | (ra != 0)) if ((rc != 0) || (ra != 0))
opc_illegal(ctx); opc_illegal(ctx);
else else
fmt_twoop_flt(ctx->instr_str, "fsqrts", rs, rb); fmt_twoop_flt(ctx->instr_str, "fsqrts", rs, rb);
@ -1462,7 +1462,7 @@ void opc_group59(PPCDisasmContext* ctx) {
if (rc_set) if (rc_set)
strcat(opcode, "."); strcat(opcode, ".");
if ((rc != 0) | (ra != 0)) if ((rc != 0) || (ra != 0))
opc_illegal(ctx); opc_illegal(ctx);
else else
fmt_twoop_flt(ctx->instr_str, opcode, rs, rb); fmt_twoop_flt(ctx->instr_str, opcode, rs, rb);
@ -1590,7 +1590,7 @@ void opc_group63(PPCDisasmContext* ctx) {
if (rc_set) if (rc_set)
strcat(opcode, "."); strcat(opcode, ".");
if ((rc != 0) | (ra != 0)) if ((rc != 0) || (ra != 0))
opc_illegal(ctx); opc_illegal(ctx);
else else
fmt_threeop_flt(ctx->instr_str, opcode, rs, ra, rb); fmt_threeop_flt(ctx->instr_str, opcode, rs, ra, rb);
@ -1627,7 +1627,7 @@ void opc_group63(PPCDisasmContext* ctx) {
if (rc_set) if (rc_set)
strcat(opcode, "."); strcat(opcode, ".");
if ((rc != 0) | (ra != 0)) if ((rc != 0) || (ra != 0))
opc_illegal(ctx); opc_illegal(ctx);
else else
ctx->instr_str = my_sprintf("%-8sf%d, f%d", opcode, rs, rb); ctx->instr_str = my_sprintf("%-8sf%d, f%d", opcode, rs, rb);
@ -1697,14 +1697,22 @@ void opc_group63(PPCDisasmContext* ctx) {
case 14: /* fctiw */ case 14: /* fctiw */
if (ra != 0) if (ra != 0)
opc_illegal(ctx); opc_illegal(ctx);
else else {
ctx->instr_str = my_sprintf("%-8s%d, r%d, r%d", "fctiw", rs, rb); strcpy(opcode, "fctiw");
if (rc_set)
strcat(opcode, ".");
ctx->instr_str = my_sprintf("%-8sf%d, f%d", opcode, rs, rb);
}
break; break;
case 15: /* fctiwz */ case 15: /* fctiwz */
if (ra != 0) if (ra != 0)
opc_illegal(ctx); opc_illegal(ctx);
else else {
ctx->instr_str = my_sprintf("%-8s%d, r%d, r%d", "fctiwz", rs, rb); strcpy(opcode, "fctiwz");
if (rc_set)
strcat(opcode, ".");
ctx->instr_str = my_sprintf("%-8sf%d, f%d", opcode, rs, rb);
}
break; break;
case 32: /* fcmpo */ case 32: /* fcmpo */
if (rs & 3) if (rs & 3)
@ -1774,7 +1782,7 @@ void opc_group63(PPCDisasmContext* ctx) {
if (rc_set) if (rc_set)
strcat(opcode, "."); strcat(opcode, ".");
if ((ra != 0) | (rb != 0)) if ((ra != 0) || (rb != 0))
opc_illegal(ctx); opc_illegal(ctx);
else else
ctx->instr_str = my_sprintf("%-8sf%d", opcode, rs); ctx->instr_str = my_sprintf("%-8sf%d", opcode, rs);

2
cpu/ppc/test/ppcdisasmtest.csv
View File

@ -367,6 +367,8 @@
0xFFF00100,0x7FF957AE,stfiwx,f31,r25,r10 0xFFF00100,0x7FF957AE,stfiwx,f31,r25,r10
0xFFF00100,0xFC40F818,frsp,f2,f31 0xFFF00100,0xFC40F818,frsp,f2,f31
0xFFF00100,0xFC201019,frsp.,f1,f2 0xFFF00100,0xFC201019,frsp.,f1,f2
0xFFF00100,0xFDA0F81E,fctiwz,f13,f31
0xFFF00100,0xFCA0501D,fctiw.,f5,f10
# compare instructions # compare instructions
0xFFF00100,0x7C15A000,cmpw,r21,r20 0xFFF00100,0x7C15A000,cmpw,r21,r20

1 # Test data for PowerPC disassembler supplied as comma-separated values
367 0xFFF00100,0xFFE0004C,mtfsb1,31 0xFFF00100,0x7FEF2C2A,lswx,r31,r15,r5
368 0xFFF00100,0xFFE0048F,mffs.,f31 0xFFF00100,0x7E000400,mcrxr,cr4
369 0xFFF00100,0x7C2000A6,mfmsr,r1 0xFFF00100,0xFFE0004C,mtfsb1,31
370 0xFFF00100,0xFFE0048F,mffs.,f31
371 0xFFF00100,0x7C2000A6,mfmsr,r1
372 0xFFF00100,0x7C000124,mtmsr,r0
373 0xFFF00100,0x7FEF01A4,mtsr,15,r31
374 0xFFF00100,0x7C6021E4,mtsrin,r3,r4