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heathrow: fix interrupt processing.

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This commit is contained in:
Maxim Poliakovski 2022-08-24 14:14:42 +02:00
parent bb77b2d525
commit 6c59bf4203
2 changed files with 29 additions and 10 deletions
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19
devices/ioctrl/heathrow.cpp
View File

@ -262,6 +262,7 @@ void HeathrowIC::mio_ctrl_write(uint32_t offset, uint32_t value, int size) {
case MIO_INT_CLEAR2:
if (value & MACIO_INT_CLR) {
this->int_events2 = 0;
clear_cpu_int();
} else {
this->int_events2 &= BYTESWAP_32(value);
}
@ -274,6 +275,7 @@ void HeathrowIC::mio_ctrl_write(uint32_t offset, uint32_t value, int size) {
case MIO_INT_CLEAR1:
if (value & MACIO_INT_CLR) {
this->int_events1 = 0;
clear_cpu_int();
} else {
this->int_events1 &= BYTESWAP_32(value);
}
@ -353,7 +355,13 @@ void HeathrowIC::ack_int(uint32_t irq_id, uint8_t irq_line_state)
}
// signal CPU interrupt
if (this->int_events1 || this->int_events2) {
ppc_ext_int();
if (!this->cpu_int_latch) {
this->cpu_int_latch = true;
ppc_assert_int();
LOG_F(5, "Heathrow: CPU INT asserted, source: %d", irq_id);
} else {
LOG_F(5, "Heathrow: CPU INT already latched");
}
}
} else {
ABORT_F("Heathrow: native interrupt mode not implemented");
@ -364,6 +372,15 @@ void HeathrowIC::ack_dma_int(uint32_t irq_id, uint8_t irq_line_state)
{
}
void HeathrowIC::clear_cpu_int()
{
if (!this->int_events1 && !this->int_events2) {
this->cpu_int_latch = false;
ppc_release_int();
LOG_F(5, "Heathrow: CPU INT latch cleared");
}
}
static const vector<string> Heathrow_Subdevices = {
"NVRAM", "ViaCuda", "Mesh", "Escc", "Swim3"
};

20
devices/ioctrl/macio.h
View File

@ -202,17 +202,19 @@ protected:
void notify_bar_change(int bar_num);
void feature_control(const uint32_t value);
void clear_cpu_int();
private:
uint32_t base_addr = 0;
uint32_t int_events2 = 0;
uint32_t int_mask2 = 0;
uint32_t int_levels2 = 0;
uint32_t int_events1 = 0;
uint32_t int_mask1 = 0;
uint32_t int_levels1 = 0;
uint32_t feat_ctrl = 0; // features control register
uint32_t aux_ctrl = 0; // aux features control register
uint32_t base_addr = 0;
uint32_t int_events2 = 0;
uint32_t int_mask2 = 0;
uint32_t int_levels2 = 0;
uint32_t int_events1 = 0;
uint32_t int_mask1 = 0;
uint32_t int_levels1 = 0;
uint32_t feat_ctrl = 0; // features control register
uint32_t aux_ctrl = 0; // aux features control register
bool cpu_int_latch = false;
uint8_t cpu_id = 0xE0; // CPUID field (LSB of the MIO_HEAT_ID)
uint8_t mb_id = 0x70; // Media Bay ID (bits 15:8 of the MIO_HEAT_ID)