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Merge pull request #104 from mihaip/upstream-mmu-perf
ppcopcodes: avoid TLB flushes for noop SR changes
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commit
6f62f9dd98
@ -728,8 +728,10 @@ void dppc_interpreter::ppc_mtsr() {
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}
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int reg_s = (ppc_cur_instruction >> 21) & 0x1F;
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uint32_t grab_sr = (ppc_cur_instruction >> 16) & 0x0F;
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if (ppc_state.sr[grab_sr] != ppc_state.gpr[reg_s]) {
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ppc_state.sr[grab_sr] = ppc_state.gpr[reg_s];
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mmu_pat_ctx_changed();
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}
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}
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void dppc_interpreter::ppc_mtsrin() {
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@ -741,8 +743,10 @@ void dppc_interpreter::ppc_mtsrin() {
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}
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ppc_grab_regssb(ppc_cur_instruction);
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uint32_t grab_sr = ppc_result_b >> 28;
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if (ppc_state.sr[grab_sr] != ppc_result_d) {
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ppc_state.sr[grab_sr] = ppc_result_d;
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mmu_pat_ctx_changed();
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}
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}
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void dppc_interpreter::ppc_mfsr() {
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@ -969,8 +973,10 @@ void dppc_interpreter::ppc_mtspr() {
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ppc_state.spr[ref_spr] = val & 0xe000ff7f;
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break;
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case SPR::SDR1:
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if (ppc_state.spr[ref_spr] != val) {
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ppc_state.spr[ref_spr] = val;
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mmu_pat_ctx_changed(); // adapt to SDR1 changes
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}
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break;
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case SPR::RTCL_S:
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calc_rtcl_value();
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@ -168,7 +168,18 @@ bool MemCtrlBase::add_mem_region(uint32_t start_addr, uint32_t size,
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entry->devobj = nullptr;
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entry->mem_ptr = reg_content;
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this->address_map.push_back(entry);
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// Keep address_map sorted, that way the RAM region (which starts at 0 and
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// is most often requested) will be found by find_range on the first
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// iteration.
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this->address_map.insert(
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std::upper_bound(
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this->address_map.begin(),
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this->address_map.end(),
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entry,
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[](const auto& lhs, const auto& rhs) {
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return lhs->start < rhs->start;
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}),
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entry);
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LOG_F(INFO, "Added mem region 0x%X..0x%X (%s%s%s%s) -> 0x%X", start_addr, end,
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entry->type & RT_ROM ? "ROM," : "",
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