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heathrow: human-readable DBDMA channel names.
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@ -117,9 +117,9 @@ void HeathrowIC::notify_bar_change(int bar_num)
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uint32_t HeathrowIC::dma_read(uint32_t offset, int size) {
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switch (offset >> 8) {
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case 1:
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case MIO_OHARE_DMA_FLOPPY:
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return this->floppy_dma->reg_read(offset & 0xFF, size);
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case 8:
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case MIO_OHARE_DMA_AUDIO_OUT:
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return this->snd_out_dma->reg_read(offset & 0xFF, size);
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default:
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LOG_F(WARNING, "Unsupported DMA channel read, offset=0x%X", offset);
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@ -130,10 +130,10 @@ uint32_t HeathrowIC::dma_read(uint32_t offset, int size) {
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void HeathrowIC::dma_write(uint32_t offset, uint32_t value, int size) {
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switch (offset >> 8) {
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case 1:
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case MIO_OHARE_DMA_FLOPPY:
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this->floppy_dma->reg_write(offset & 0xFF, value, size);
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break;
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case 8:
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case MIO_OHARE_DMA_AUDIO_OUT:
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this->snd_out_dma->reg_write(offset & 0xFF, value, size);
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break;
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default:
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@ -40,7 +40,7 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
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DMA space. Access to emulated legacy devices is accomplished by reading from/
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writing to MIO's PCI address space at predefined offsets.
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MIO includes a DMA controller that offers 15 DMA channels implementing
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MIO includes a DMA controller that offers up to 12 DMA channels implementing
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Apple's own DMA protocol called descriptor-based DMA (DBDMA).
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Official documentation (that is somewhat incomplete and erroneous) can be
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@ -219,6 +219,22 @@ enum {
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MIO_OHARE_FEAT_CTRL = 0x38, // feature control register
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};
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/** O'Hare/Heathrow DBDMA channels. */
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enum : uint8_t {
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MIO_OHARE_DMA_MESH = 0,
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MIO_OHARE_DMA_FLOPPY = 1,
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MIO_OHARE_DMA_ETH_XMIT = 2,
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MIO_OHARE_DMA_ETH_RCV = 3,
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MIO_OHARE_DMA_ESSC_A_XMIT = 4,
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MIO_OHARE_DMA_ESSC_A_RCV = 5,
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MIO_OHARE_DMA_ESSC_B_XMIT = 6,
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MIO_OHARE_DMA_ESSC_B_RCV = 7,
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MIO_OHARE_DMA_AUDIO_OUT = 8,
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MIO_OHARE_DMA_AUDIO_IN = 9,
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MIO_OHARE_DMA_IDE0 = 0xB,
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MIO_OHARE_DMA_IDE1 = 0xC
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};
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class HeathrowIC : public PCIDevice, public InterruptCtrl {
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public:
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HeathrowIC();
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