mirror of
https://github.com/dingusdev/dingusppc.git
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New base class for SCSI host controllers.
This commit is contained in:
Maxim Poliakovski
parent
f13f4e0023
commit
889dc32a0a
290
devices/common/scsi/scsibusctrl.cpp
Normal file
290
devices/common/scsi/scsibusctrl.cpp
Normal file
@ -0,0 +1,290 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file SCSI bus controller emulation. */
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#include <core/timermanager.h>
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#include <devices/common/scsi/scsibusctrl.h>
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#include <loguru.hpp>
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#include <cinttypes>
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#include <cstring>
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using namespace Scsi_Bus_Controller;
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void ScsiBusController::seq_defer_state(uint64_t delay_ns) {
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seq_timer_id = TimerManager::get_instance()->add_oneshot_timer(
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delay_ns,
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[this]() {
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// re-enter the sequencer with the state specified in next_state
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this->cur_state = this->next_state;
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this->sequencer();
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});
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}
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void ScsiBusController::sequencer() {
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switch (this->cur_state) {
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case SeqState::IDLE:
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break;
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case SeqState::BUS_FREE:
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if (this->bus_obj->current_phase() == ScsiPhase::BUS_FREE) {
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this->next_state = SeqState::ARB_BEGIN;
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this->seq_defer_state(BUS_FREE_DELAY + BUS_SETTLE_DELAY);
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} else { // continue waiting
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this->next_state = SeqState::BUS_FREE;
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this->seq_defer_state(BUS_FREE_DELAY);
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}
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break;
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case SeqState::ARB_BEGIN:
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if (!this->bus_obj->begin_arbitration(this->src_id)) {
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LOG_F(ERROR, "%s: arbitration error, bus not free!", this->name.c_str());
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this->bus_obj->release_ctrl_lines(this->src_id);
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this->next_state = SeqState::BUS_FREE;
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this->seq_defer_state(BUS_CLEAR_DELAY);
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break;
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}
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this->next_state = SeqState::ARB_END;
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this->seq_defer_state(ARB_DELAY);
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break;
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case SeqState::ARB_END:
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if (this->bus_obj->end_arbitration(this->src_id) &&
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!this->bus_obj->test_ctrl_lines(SCSI_CTRL_SEL)) { // arbitration won
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this->bus_obj->assert_ctrl_line(this->src_id, SCSI_CTRL_SEL);
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this->step_completed();
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} else { // arbitration lost
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LOG_F(ERROR, "%s: arbitration lost!", this->name.c_str());
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this->bus_obj->release_ctrl_lines(this->src_id);
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this->report_error(ARB_LOST);
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}
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break;
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case SeqState::SEL_BEGIN:
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this->bus_obj->begin_selection(this->src_id, this->dst_id, this->assert_atn);
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this->next_state = SeqState::SEL_END;
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this->seq_defer_state(SEL_TIME_OUT);
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break;
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case SeqState::SEL_END:
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if (this->bus_obj->end_selection(this->src_id, this->dst_id)) {
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this->bus_obj->release_ctrl_line(this->src_id, SCSI_CTRL_SEL);
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LOG_F(9, "%s: selection completed", this->name.c_str());
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this->step_completed();
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} else { // selection timeout
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this->bus_obj->disconnect(this->src_id);
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this->cur_state = SeqState::IDLE;
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this->report_error(SEL_TIMEOUT);
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}
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break;
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case SeqState::SEND_MSG:
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if (this->fifo_pos) {
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this->bus_obj->target_xfer_data();
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this->bus_obj->release_ctrl_line(this->src_id, SCSI_CTRL_ATN);
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if (this->to_xfer <= 0)
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this->step_completed();
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}
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break;
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case SeqState::SEND_CMD:
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this->bus_obj->target_xfer_data();
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if (!this->fifo_pos)
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this->step_completed();
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break;
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case SeqState::XFER_BEGIN:
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this->cur_bus_phase = this->bus_obj->current_phase();
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switch (this->cur_bus_phase) {
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case ScsiPhase::DATA_OUT:
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this->cur_state = SeqState::SEND_DATA;
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break;
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case ScsiPhase::DATA_IN:
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this->bus_obj->negotiate_xfer(this->fifo_pos, this->bytes_out);
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this->cur_state = SeqState::RCV_DATA;
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this->rcv_data();
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}
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break;
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case SeqState::XFER_END:
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if (this->is_initiator)
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this->bus_obj->target_next_step();
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this->step_completed();
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break;
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case SeqState::SEND_DATA:
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if (this->bus_obj->push_data(this->dst_id, this->data_fifo, this->fifo_pos)) {
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this->to_xfer -= this->fifo_pos;
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this->fifo_pos = 0;
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if (this->to_xfer <= 0) {
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this->cur_state = SeqState::XFER_END;
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this->sequencer();
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}
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}
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break;
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case SeqState::RCV_DATA:
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// check for unexpected bus phase changes
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if (this->bus_obj->current_phase() != this->cur_bus_phase) {
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LOG_F(WARNING, "%s: phase mismatch!", this->name.c_str());
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} else {
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if (!this->rcv_data()) {
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this->cur_state = SeqState::XFER_END;
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this->sequencer();
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}
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}
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break;
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case SeqState::RCV_STATUS:
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case SeqState::RCV_MESSAGE:
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this->bus_obj->negotiate_xfer(this->fifo_pos, this->bytes_out);
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this->rcv_data();
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if (this->is_initiator) {
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if (this->cur_state == SeqState::RCV_MESSAGE)
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this->bus_obj->assert_ctrl_line(this->src_id, SCSI_CTRL_ACK);
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this->bus_obj->target_next_step();
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this->step_completed();
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this->cur_state = SeqState::IDLE;
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}
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break;
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default:
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ABORT_F("%s: unimplemented sequencer state %d", this->name.c_str(),
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this->cur_state);
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}
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}
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void ScsiBusController::notify(ScsiMsg msg_type, int param) {
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switch (msg_type) {
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case ScsiMsg::CONFIRM_SEL:
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if (this->dst_id == param) {
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// cancel selection timeout timer
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TimerManager::get_instance()->cancel_timer(this->seq_timer_id);
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seq_timer_id = 0;
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this->cur_state = SeqState::SEL_END;
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this->sequencer();
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} else {
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LOG_F(WARNING, "%s: ignore invalid selection confirmation message",
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this->name.c_str());
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}
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break;
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case ScsiMsg::BUS_PHASE_CHANGE:
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this->cur_bus_phase = param;
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#if 0
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if (param != ScsiPhase::BUS_FREE && this->cmd_steps != nullptr) {
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this->cmd_steps++;
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this->cur_state = this->cmd_steps->next_step;
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this->sequencer();
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}
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#endif
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break;
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default:
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LOG_F(9, "%s: ignore notification message, type: %d", this->name.c_str(),
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msg_type);
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}
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}
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bool ScsiBusController::rcv_data() {
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int req_count;
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// return if REQ line is negated
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if (!this->bus_obj->test_ctrl_lines(SCSI_CTRL_REQ)) {
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return false;
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}
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if (!this->to_xfer)
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return false;
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req_count = std::min(this->to_xfer, DATA_FIFO_DEPTH - this->fifo_pos);
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this->bus_obj->pull_data(this->dst_id, &this->data_fifo[this->fifo_pos], req_count);
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this->fifo_pos += req_count;
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this->to_xfer -= req_count;
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return true;
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}
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int ScsiBusController::send_data(uint8_t* dst_ptr, int count) {
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if (dst_ptr == nullptr || !count)
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return 0;
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int actual_count = std::min(this->fifo_pos, count);
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// move data out of the data FIFO
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std::memcpy(dst_ptr, this->data_fifo, actual_count);
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// remove the just readed data from the data FIFO
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this->fifo_pos -= actual_count;
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this->to_xfer -= actual_count;
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if (this->fifo_pos > 0)
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std::memmove(this->data_fifo, &this->data_fifo[actual_count], this->fifo_pos);
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return actual_count;
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}
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int ScsiBusController::xfer_from(uint8_t *buf, int len) {
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if (len > this->to_xfer + this->fifo_pos)
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LOG_F(WARNING, "%s: DMA xfer len > command xfer len", this->name.c_str());
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if (this->fifo_pos) {
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int fifo_bytes = std::min(this->fifo_pos, len);
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std::memcpy(buf, this->data_fifo, fifo_bytes);
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this->fifo_pos -= fifo_bytes;
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len -= fifo_bytes;
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buf += fifo_bytes;
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}
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int dma_bytes = std::min(this->to_xfer, len);
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if (this->bus_obj->pull_data(this->dst_id, buf, dma_bytes)) {
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this->to_xfer -= dma_bytes;
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if (this->to_xfer <= 0) {
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this->xfer_count = this->to_xfer;
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this->cur_state = SeqState::XFER_END;
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this->sequencer();
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}
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return 0;
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}
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return len;
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}
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void ScsiBusController::update_irq() {
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uint8_t new_irq = !!(this->int_stat & this->int_mask);
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if (new_irq != this->irq) {
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this->irq = new_irq;
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this->int_ctrl->ack_int(this->irq_id, new_irq);
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}
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}
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void ScsiBusController::fifo_push(const uint8_t data) {
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if (this->fifo_pos < DATA_FIFO_DEPTH) {
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this->data_fifo[this->fifo_pos++] = data;
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if (!this->xfer_count)
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LOG_F(WARNING, "%s: zero xfer_count!", this->name.c_str());
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if (--this->xfer_count == 0)
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this->sequencer();
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} else
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this->sequencer();
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}
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uint8_t ScsiBusController::fifo_pop() {
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uint8_t data = 0;
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if (this->fifo_pos) {
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data = this->data_fifo[0];
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if (--this->fifo_pos)
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std:memmove(this->data_fifo, &this->data_fifo[1], this->fifo_pos);
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}
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// see if we need to refill FIFO
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if (!this->fifo_pos)
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this->sequencer();
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return data;
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}
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122
devices/common/scsi/scsibusctrl.h
Normal file
122
devices/common/scsi/scsibusctrl.h
Normal file
@ -0,0 +1,122 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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||||
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file SCSI bus controller definitions. */
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#ifndef SCSI_BUS_CTRL_H
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#define SCSI_BUS_CTRL_H
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#include <devices/common/dmacore.h>
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#include <devices/common/hwinterrupt.h>
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#include <devices/common/scsi/scsi.h>
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#include <cinttypes>
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#include <string>
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namespace Scsi_Bus_Controller {
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/** SCSI sequencer states. */
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enum SeqState : uint32_t {
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IDLE = 0,
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BUS_FREE,
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ARB_BEGIN,
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ARB_END,
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SEL_BEGIN,
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SEL_END,
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SEND_MSG,
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SEND_CMD,
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CMD_COMPLETE,
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XFER_BEGIN,
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XFER_END,
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SEND_DATA,
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RCV_DATA,
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RCV_STATUS,
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RCV_MESSAGE,
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};
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};
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/** Sequencer error codes. */
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enum : int {
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ARB_LOST = 1,
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SEL_TIMEOUT,
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};
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#define DATA_FIFO_DEPTH 16
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class ScsiBusController : public ScsiDevice, public DmaDevice {
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public:
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ScsiBusController(std::string name, uint8_t my_bus_id=7) : ScsiDevice(name, my_bus_id) {
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supports_types(HWCompType::SCSI_HOST | HWCompType::SCSI_DEV);
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}
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~ScsiBusController() = default;
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// implements SCSI FSM
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void sequencer();
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virtual void step_completed() = 0;
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virtual void report_error(const int error) = 0;
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// ScsiDevice methods
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void notify(ScsiMsg msg_type, int param);
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bool prepare_data() { return false; };
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bool get_more_data() { return false; };
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bool has_data() { return false; };
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bool rcv_data();
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int send_data(uint8_t* dst_ptr, int count);
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void process_command() {};
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// DmaDevice methods
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int xfer_from(uint8_t *buf, int len); // must be marked OVERRIDE!
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protected:
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void seq_defer_state(uint64_t delay_ns);
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void update_irq();
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void fifo_push(const uint8_t data);
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uint8_t fifo_pop();
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ScsiBus* bus_obj = nullptr;
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uint8_t src_id;
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uint8_t dst_id;
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bool is_dma_cmd = false;
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bool is_initiator = true;
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bool assert_atn = false;
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// Data FIFO state
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int fifo_pos = 0;
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int to_xfer = 0;
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uint32_t xfer_count = 0;
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int bytes_out = 0;
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uint8_t data_fifo[DATA_FIFO_DEPTH] = {};
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// Sequencer state
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uint32_t seq_timer_id = 0;
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uint32_t cur_state = Scsi_Bus_Controller::SeqState::IDLE;
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uint32_t next_state = Scsi_Bus_Controller::SeqState::IDLE;
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int cur_bus_phase = 0;
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// interrupt related stuff
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InterruptCtrl* int_ctrl = nullptr;
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uint32_t irq_id = 0;
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uint8_t irq = 0;
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uint8_t int_mask = 0;
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uint8_t int_stat = 0;
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};
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#endif // SCSI_BUS_CTRL_H
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