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zdocs: rewamp Heathrow doc, part 1.
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Maxim Poliakovski
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The Heathrow is an I/O subsystem and a DMA controller.
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# Heathrow ASIC
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It contains a feature control register, an auxiliary control register, and some registers to save states for the DBDMA and the VIA Cuda.
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The Heathrow ASIC is an intergrated I/O controller designed for use in Power
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Macintosh G3 computers.
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It also contains the emulations for the VIA Cuda, SWIM 3 floppy drive, ESCC, and MESH components.
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Its predecessors are Grand Central and O'Hare ASICs used in other Power Macintosh
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computers. As those names suggest, Apple engineers liked to name their I/O controllers
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after airports and train stations.
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# Register Map
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| Register Name | Offset |
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|:-------------------:|:------:|
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| Interrupt Events 2 | 0x10 |
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| Interrupt Mask 2 | 0x14 |
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| Interrupt Clear 2 | 0x18 |
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| Interrupt Levels 2 | 0x1C |
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| Interrupt Events 1 | 0x20 |
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| Interrupt Mask 1 | 0x24 |
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| Interrupt Clear 1 | 0x28 |
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| Interrupt Levels 1 | 0x2C |
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| Chassis Light Color | 0x32 |
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| Media Bay Control | 0x34 |
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| Feature Control | 0x38 |
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| Auxiliary Control | 0x3C |
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Heathrow and its siblings are collectively referred to as __mac-io__ devices in the
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OpenFirmware device tree.
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## Mac I/O family
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The purpose of a Mac I/O (MIO) controller is to bring support for Apple legacy
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I/O hardware to the PCI-based Power Macintosh. That legacy hardware has
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existed long before Power Macintosh was introduced. It includes:
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- versatile interface adapter (VIA)
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- Sander-Woz integrated machine (SWIM) that is a floppy disk controller
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- CUDA MCU that controls ADB, parameter RAM, realtime clock and power management
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- serial communication controller (SCC)
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- Macintosh Enhanced SCSI Hardware (MESH)
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In the 68k Macintosh era, all this hardware was implemented in separate ICs.
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In a PCI-compatible Power Macintosh, the above devices are part
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of the MIO chip itself. MIO's functional blocks implementing the above devices
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are called __cells__, i.e. "VIA cell", "SWIM cell" etc.
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MIO itself is PCI compliant while the legacy hardware it emulates isn't.
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MIO occupies 512Kb of the PCI memory space divided into registers space and
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DMA space. Access to emulated legacy devices is accomplished by reading from/
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writing to MIO's PCI address space at predefined offsets.
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MIO includes a DMA controller that offers 15 DMA channels implementing
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Apple's own DMA protocol called descriptor-based DMA (DBDMA).
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Official documentation (that is somewhat incomplete and erroneous) can be
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found in the second chapter of the book "Macintosh Technology in the Common
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Hardware Reference Platform" by Apple Computer, Inc.
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## Heathrow I/O modules
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Being a Mac I/O compatible device, the Heathrow ASIC contains the following modules/cells:
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* VIA cell for establishing communication with the Cuda MCU (separate IC)
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* ATA/IDE cell for controlling ATA-3 compatible drives
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* enhanced serial communication controller (ESCC cell)
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* Ethernet controller cell funnily called __bmac__
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* floppy disk controller (SWIM3 cell)
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* SCSI controller (MESH cell)
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* integrated DBDMA controller
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* interrupt controller
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* logic for controlling built-in audio HW
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* logic for accessing NVRAM (separate IC)
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* logic for controlling a media bay on portables
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## PCI configuration space registers
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| Register name | Default value |
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|:-------------:|:--------------:|
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| VendorID | 0x106B (Apple) |
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| DeviceID | 0x0010 |
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| RevisionID | 0x01 |
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| Class code | 0xFF0000 |
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It looks like Heathrow supports only one Base Address Register - __BAR0__.
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It contains base address of the memory-mapped registers programmed by system software
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during system initialization.
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## Memory-mapped registers
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Software communicates with the Heathrow ASIC via memory-mapped registers that
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occupy 512 Kb starting from the base address located in the BAR0 register
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in the PCI configuration space.
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Macintosh firmware configures the Heathrow ASIC to live at address `0xF3000000`.
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### General chip control registers
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| Offset | Register name | Description |
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|:------:|:-----------------:|:----------------------------------------------:|
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| 0x10 | InterruptEvents2 | each "1" bit indicates a pending int |
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| 0x14 | InterruptMask2 | enabling (1) / disabling(0) of specific ints |
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| 0x18 | InterruptClear2 | bit value "1" clears the corresponding int |
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| 0x1C | InterruptLevels2 | interrupt status for devices 32...63 |
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| 0x20 | InterruptEvents1 | each "1" bit indicates a pending int |
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| 0x24 | InterruptMask1 | enabling (1) / disabling(0) of specific ints |
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| 0x28 | InterruptClear1 | bit value "1" clears the corresponding int |
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| 0x2C | InterruptLevels1 | interrupt status for devices 0...31 |
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| 0x30 | UnknownReg30 | Not much is known about this register |
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| 0x34 | HeathrowIDs | bits for identifying media bay features? |
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| 0x38 | FeatureControl | bits for controlling Heathrow operation |
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| 0x3C | AuxControl | auxilary control bits |
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### Device DMA spaces
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| Offset | Size in bytes | Space name |
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|:------:|:-------------:|:-----------------------------:|
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| 0x8000 | 256 | MESH SCSI DMA |
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| 0x8100 | 256 | Floppy controller DMA |
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| 0x8200 | 256 | Ethernet transmit DMA |
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| 0x8300 | 256 | Ethernet receive DMA |
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| 0x8400 | 256 | Serial channel A transmit DMA |
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| 0x8500 | 256 | Serial channel A receive DMA |
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| 0x8600 | 256 | Serial channel B transmit DMA |
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| 0x8700 | 256 | Serial channel B receive DMA |
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| 0x8800 | 256 | Audio output DMA |
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| 0x8900 | 256 | Audio input DMA |
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| 0x8A00 | 256 | unassigned DMA ? |
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| 0x8B00 | 256 | internal ATA (IDE0) DMA |
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| 0x8C00 | 256 | media bay (?) ATA (IDE1) DMA |
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| 0x8D00 | 256 | unassigned DMA ? |
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| 0x8E00 | 256 | unassigned DMA ? |
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| 0x8F00 | 256 | unassigned DMA ? |
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### Device register spaces
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| Offset | Size | Space name |
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|:--------|------------- :|:----------------------------------------:|
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| 0x10000 | 4 KB | MESH SCSI controller registers |
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| 0x11000 | 4 KB | Ethernet (bmac) controller registers |
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| 0x12000 | 4 KB | Legacy serial (SCC) controller registers |
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| 0x13000 | 4 KB | Serial (ESCC) controller registers |
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| 0x14000 | 4 KB | Audio codec registers |
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| 0x15000 | 4 KB | Floppy (SWIM3) controller registers |
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| 0x16000 | 8 KB | VIA registers |
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| 0x20000 | 4 KB | IDE0 registers |
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| 0x21000 | 4 KB | IDE1 registers |
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| 0x60000 | 128 KB | NVRAM access |
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## Registers description
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### General chip control
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#### Feature control register
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Bit names in the table below were pulled from OpenFirmware v2.4.
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The field "Description" represents my personal attempt to describe the function
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of those bits based on publicly available Apple and Linux sources.
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| Bit # | Active | Name | Description |
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|:-----:|:------:|:-------------:|:---------------------------------------:|
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| 0 | high | in_use_led | "1" enables monitor sense on G3 desktop |
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| 1 | low | -mb_pwr | media bay power on/off |
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| 2 | high | pci_mb_en | enable media bay PCI (?) |
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| 3 | high | ide_mb_en | enable media bay ATA (IDE1) |
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| 4 | high | floppy_en | enable floppy disk controller cell |
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| 5 | high | ide_int_en | enable internal ATA (IDE0) |
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| 6 | low | -ide0_reset | reset internal ATA |
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| 7 | low | -mb_reset | reset media bay |
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| 8 | high | iobus_enable | *not available* |
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| 9 | high | scc_enable | enable SCC controller cell |
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| 10 | high | scsi_cell_en | enable MESH SCSI controller cell |
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| 11 | high | swim_cell_en | enable SWIM3 floppy controller cell |
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| 12 | high | snd_pwr | *not available* |
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| 13 | high | snd_clk_en | enable sound chip clock (?) |
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| 14 | high | scc_a_enable | enable SCC channel A |
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| 15 | high | scc_b_enable | enable SCC channel B |
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| 16 | low | -port_via | switch VIA cell to portable mode (?) |
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| 16 | high | desktop_via | switch VIA cell to desktop mode (?) |
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| 17 | low | -pwm | *not available* |
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| 17 | high | mon_id | *not available* |
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| 18 | low | -hookpb | *not available* |
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| 18 | high | mb_cnt | *not available* |
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| 19 | low | -swimiii | floppy controller in SWIM3 mode (?) |
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| 19 | high | clonefloppy | floppy controller in PC-compat mode (?) |
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| 20 | high | aud22run | *not available* |
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| 21 | high | scsi_linkmode | *not available* |
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| 22 | high | arb_bypass | disable internal PCI arbiter (?) |
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| 23 | low | -ide1_reset | reset media bay ATA |
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| 24 | high | slow_scc_pclk | *not available* |
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| 25 | high | reset_scc | reset serial (SCC) controller cell |
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| 26 | high | mfdc_cell_en | enable PC-compat floppy controller (?) |
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| 27 | high | use_mfdc | use PC floppy ctrl instead of SWIM3 ? |
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| 29 | high | enet_ctrl_en | enable Ethernet controller cell (?) |
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| 30 | high | enet_xcvr_en | enable Ethernet Transceiver (?) |
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| 31 | high | enet_reset | reset Ethernet cell |
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