From 916cb47b9d52852462b07c4498e1e4c39252581e Mon Sep 17 00:00:00 2001
From: joevt <joevt@shaw.ca>
Date: Tue, 9 Apr 2024 02:47:03 -0700
Subject: [PATCH] poweropcodes: Fix srlq.

Test bit 26 of rB instead of testing for >= 0x20 to determine which operation to perform.
---
 cpu/ppc/poweropcodes.cpp | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/cpu/ppc/poweropcodes.cpp b/cpu/ppc/poweropcodes.cpp
index dda0c41..4ae09ec 100644
--- a/cpu/ppc/poweropcodes.cpp
+++ b/cpu/ppc/poweropcodes.cpp
@@ -642,10 +642,9 @@ void dppc_interpreter::power_srlq() {
     uint32_t r      = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
     unsigned mask   = power_rot_mask(rot_sh, 31);
 
-    if (ppc_result_b >= 0x20) {
+    if (ppc_result_b & 0x20) {
         ppc_result_a = (ppc_state.spr[SPR::MQ] & mask);
-    }
-    else {
+    } else {
         ppc_result_a = ((r & mask) | (ppc_state.spr[SPR::MQ] & ~mask));
     }