Macintosh-Tools/dingusppc
1
0
Fork 0
mirror of https://github.com/dingusdev/dingusppc.git synced 2025-01-11 05:29:43 +00:00
Code Issues Projects Releases Wiki Activity

Prevents the non-trivial array initialization error

Browse Source 
A touch haphazard, but this allows most compilers to interpret this array.
This commit is contained in:
dingusdev 2019-10-15 21:19:00 -07:00 committed by GitHub
parent e7564ab0a5
commit 97e87dea9e
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 83 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

93
devices/mpc106.h
View File

@ -70,16 +70,89 @@ private:
0x00, // standard programming
0x00, // subclass code: host bridge
0x06, // class code: bridge device
[0x73] = 0xCD, // default value for ODCR
[0xA8] = 0x10, 0x00, 0x00, 0xFF, // PICR1
[0xAC] = 0x0C, 0x06, 0x0C, 0x00, // PICR2
[0xBA] = 0x04,
[0xC0] = 0x01,
[0xE0] = 0x42, 0x00, 0xFF, 0x0F,
[0xE8] = 0x20,
[0xF0] = 0x00, 0x00, 0x02, 0xFF,
[0xF4] = 0x03,
[0xFC] = 0x00, 0x00, 0x10, 0x00
0x08, // cache line size
0x00, // latency timer
0x00, // header type
0x00, // BIST Control
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0x00, //Interrupt line
0x00, //Interrupt pin
0x00, //MIN GNT
0x00, //MAX LAT
0x00, //Bus number
0x00, //Subordinate bus number
0x00, //Discount counter
0x00, //MAX LAT
0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0x00, 0x00, 0x00, 0x00, //Performance monitor command
0x00, 0x00, //Performance monitor mode control
0xFF, 0xFF,
0x00, 0x00, 0x00, 0x00, //Performance monitor counter 0
0x00, 0x00, 0x00, 0x00, //Performance monitor counter 1
0x00, 0x00, 0x00, 0x00, //Performance monitor counter 2
0x00, 0x00, 0x00, 0x00, //Performance monitor counter 3
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0x00, 0x00, //Power mgt config 1
0x00, //Power mgt config 2
0xCD, //default value for ODCR
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //Memory Starting Address
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //Extended Memory Starting Address
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //Memory Ending Address
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //Extended Memory Ending Address
0x00, //Memory bank enable
0xFF, 0xFF,
0x00, //Memory page mode
0xFF, 0xFF, 0xFF, 0xFF,
0x10, 0x00, 0x00, 0xFF, // PICR1
0x0C, 0x06, 0x0C, 0x00, // PICR2
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0x00, //ECC single-bit error counter
0x00, //ECC single-bit error trigger
0x04, //Alternate OS visible paramaters 1
0x01, //Alternate OS visible paramaters 2
0xFF, 0xFF, 0xFF, 0xFF,
0x01, //Error enabling 1
0x00, //Error detection 1
0xFF,
0x00, //60x bus error status
0x00, //Error enabling 2
0x00, //Error detection 2
0xFF,
0x00, //PCI bus error status
0x00, 0x00, 0x00, 0x00, //60x/PCI ERROR address
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0x42, 0x00, 0xFF, 0x0F, //Emulation support config 1
0x00, 0x00, 0x00, 0x00, //Modified memory status (no clear)
0x20, 0x00, 0x00, 0x00, //Emulation support config 2
0x00, 0x00, 0x00, 0x00, //Modified memory status (clear)
0x00, 0x00, 0x02, 0xFF, //Memory ctrl config 1
0x03, 0x00, 0x00, 0x00, //Memory ctrl config 2
0x00, 0x00, 0x00, 0x00, //Memory ctrl config 3
0x00, 0x00, 0x10, 0x00 //Memory ctrl config 4
};
uint32_t config_addr;