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Optimize register initialization
Courtesy of joevt, adapted to fit the C++ standard
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@ -799,23 +799,15 @@ void initialize_ppc_opcode_tables() {
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}
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}
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}
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}
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void ppc_fpu_init() {
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// zero all FPRs as prescribed for MPC601
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// For later PPC CPUs, GPR content is undefined
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for (int i = 0; i < 32; i++) {
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ppc_state.fpr[i].int64_r = 0;
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}
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ppc_state.fpscr = 0;
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set_host_rounding_mode(0);
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}
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void ppc_cpu_init(MemCtrlBase* mem_ctrl, uint32_t cpu_version, uint64_t tb_freq)
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void ppc_cpu_init(MemCtrlBase* mem_ctrl, uint32_t cpu_version, uint64_t tb_freq)
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{
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{
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int i;
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int i;
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mem_ctrl_instance = mem_ctrl;
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mem_ctrl_instance = mem_ctrl;
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std::memset(&ppc_state, 0, sizeof(ppc_state));
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set_host_rounding_mode(0);
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ppc_state.spr[SPR::PVR] = cpu_version;
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ppc_state.spr[SPR::PVR] = cpu_version;
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is_601 = (cpu_version >> 16) == 1;
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is_601 = (cpu_version >> 16) == 1;
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@ -862,31 +854,6 @@ void ppc_cpu_init(MemCtrlBase* mem_ctrl, uint32_t cpu_version, uint64_t tb_freq)
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timebase_counter = 0;
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timebase_counter = 0;
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dec_wr_value = 0;
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dec_wr_value = 0;
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/* zero all GPRs as prescribed for MPC601 */
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/* For later PPC CPUs, GPR content is undefined */
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for (i = 0; i < 32; i++) {
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ppc_state.gpr[i] = 0;
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}
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/* zero all segment registers as prescribed for MPC601 */
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/* For later PPC CPUs, SR content is undefined */
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for (i = 0; i < 16; i++) {
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ppc_state.sr[i] = 0;
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}
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ppc_state.cr = 0;
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ppc_fpu_init();
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ppc_state.pc = 0;
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ppc_state.tbr[0] = 0;
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ppc_state.tbr[1] = 0;
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/* zero all SPRs */
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for (i = 0; i < 1024; i++) {
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ppc_state.spr[i] = 0;
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}
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if (is_601) {
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if (is_601) {
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/* MPC601 sets MSR[ME] bit during hard reset / Power-On */
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/* MPC601 sets MSR[ME] bit during hard reset / Power-On */
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