From a4eb658309d16144d4048f1021838557d9fd878d Mon Sep 17 00:00:00 2001 From: Maxim Poliakovski Date: Fri, 5 Feb 2021 02:01:31 +0100 Subject: [PATCH] atirage: increase PLL registers count to 64. --- devices/atirage.cpp | 7 ++++--- devices/atirage.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/devices/atirage.cpp b/devices/atirage.cpp index b6f6940..a0a915e 100644 --- a/devices/atirage.cpp +++ b/devices/atirage.cpp @@ -125,10 +125,10 @@ uint32_t ATIRage::read_reg(uint32_t offset, uint32_t size) { case ATI_GP_IO: break; case ATI_CLOCK_CNTL: + /* reading from internal PLL registers */ if (offset == ATI_CLOCK_CNTL+2 && size == 1 && !(this->block_io_regs[ATI_CLOCK_CNTL+1] & 0x2)) { - int pll_addr = this->block_io_regs[ATI_CLOCK_CNTL+1] >> 2; - return this->plls[pll_addr & 0xF]; + return this->plls[this->block_io_regs[ATI_CLOCK_CNTL+1] >> 2]; } break; case ATI_DAC_REGS: @@ -186,11 +186,12 @@ void ATIRage::write_reg(uint32_t offset, uint32_t value, uint32_t size) { } break; case ATI_CLOCK_CNTL: + /* writing to internal PLL registers */ if (offset == ATI_CLOCK_CNTL+2 && size == 1 && (this->block_io_regs[ATI_CLOCK_CNTL+1] & 0x2)) { int pll_addr = this->block_io_regs[ATI_CLOCK_CNTL+1] >> 2; uint8_t pll_data = this->block_io_regs[ATI_CLOCK_CNTL+2]; - this->plls[pll_addr & 0xF] = pll_data; + this->plls[pll_addr] = pll_data; LOG_F(INFO, "ATI Rage: PLL #%d set to 0x%02X", pll_addr, pll_data); } break; diff --git a/devices/atirage.h b/devices/atirage.h index a74d147..0cfd89e 100644 --- a/devices/atirage.h +++ b/devices/atirage.h @@ -217,7 +217,7 @@ private: uint8_t pci_cfg[256] = {0}; /* PCI configuration space */ - uint8_t plls[16] = {0}; // internal PLL registers + uint8_t plls[64] = {0}; // internal PLL registers /* Video RAM variables */ uint32_t vram_size;