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Refactor ATA/IDE classes.
This commit is contained in:
parent
58908621e6
commit
a892842b8f
@ -1,37 +0,0 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file Heathrow hard drive controller */
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#include <devices/deviceregistry.h>
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#include <devices/common/ata/ata_bus.h>
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#include <fstream>
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#include <limits>
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#include <stdio.h>
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#include <loguru.hpp>
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#define sector_size 512
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using namespace std;
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AtaBus::AtaBus() {
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supports_types(HWCompType::IDE_BUS);
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}
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@ -1,64 +0,0 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
|
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the Free Software Foundation, either version 3 of the License, or
|
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file Null ATA device */
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#include <devices/common/ata/ata_null.h>
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#include <devices/deviceregistry.h>
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#include <cinttypes>
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#include <fstream>
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#include <loguru.hpp>
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AtaNullDevice::AtaNullDevice() {
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supports_types(HWCompType::IDE_DEV);
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regs[IDE_Reg::STATUS] = IDE_Status::DRDY | IDE_Status::DSC;
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regs[IDE_Reg::ALT_STATUS] = IDE_Status::DRDY | IDE_Status::DSC;
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}
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uint32_t AtaNullDevice::read(int reg) {
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if (reg == IDE_Reg::ERROR) {
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return IDE_Error::TK0NF;
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}
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else if (reg == IDE_Reg::STATUS) {
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return IDE_Status::ERR;
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}
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LOG_F(WARNING, "Dummy read for IDE register 0x%x", reg);
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return 0x0;
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}
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void AtaNullDevice::write(int reg, uint32_t value) {
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if (reg == IDE_Reg::COMMAND) {
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process_command(value);
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}
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LOG_F(WARNING, "Dummy write for IDE register 0x%x with value 0x%x", reg, value);
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}
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int AtaNullDevice::process_command(uint32_t cmd) {
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LOG_F(ERROR, "Attempted to execute command %x", cmd);
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return 0;
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}
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static const DeviceDescription ATA_Null_Descriptor = {
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AtaNullDevice::create, {}, {}
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};
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REGISTER_DEVICE(AtaNullDevice, ATA_Null_Descriptor);
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@ -21,18 +21,20 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
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/** @file Heathrow hard drive controller */
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/** @file Heathrow hard drive controller */
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#include <devices/common/ata/ata_full.h>
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#include <devices/common/ata/atabasedevice.h>
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#include <devices/common/ata/atadefs.h>
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#include <devices/deviceregistry.h>
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#include <devices/deviceregistry.h>
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#include <fstream>
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#include <limits>
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#include <loguru.hpp>
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#include <loguru.hpp>
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#include <stdio.h>
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#include <cinttypes>
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#define sector_size 512
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#define sector_size 512
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using namespace std;
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using namespace std;
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AtaFullDevice::AtaFullDevice() {
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AtaBaseDevice::AtaBaseDevice(const std::string name)
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{
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this->set_name(name);
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supports_types(HWCompType::IDE_DEV);
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supports_types(HWCompType::IDE_DEV);
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regs[IDE_Reg::ERROR] = IDE_Error::ANMF;
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regs[IDE_Reg::ERROR] = IDE_Error::ANMF;
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@ -42,19 +44,8 @@ AtaFullDevice::AtaFullDevice() {
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regs[IDE_Reg::ALT_STATUS] = IDE_Status::DRDY | IDE_Status::DSC;
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regs[IDE_Reg::ALT_STATUS] = IDE_Status::DRDY | IDE_Status::DSC;
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}
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}
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void AtaFullDevice::insert_image(std::string filename) {
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uint16_t AtaBaseDevice::read(const uint8_t reg_addr) {
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this->ide_img.open(filename, ios::out | ios::in | ios::binary);
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switch (reg_addr) {
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// Taken from:
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// https://stackoverflow.com/questions/22984956/tellg-function-give-wrong-size-of-file/22986486
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ide_img.ignore(std::numeric_limits<std::streamsize>::max());
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img_size = this->ide_img.gcount();
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ide_img.clear(); // Since ignore will have set eof.
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ide_img.seekg(0, std::ios_base::beg);
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}
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uint32_t AtaFullDevice::read(int reg) {
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switch (reg) {
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case IDE_Reg::IDE_DATA:
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case IDE_Reg::IDE_DATA:
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LOG_F(0, "Retrieving DATA from IDE: %x", regs[IDE_Reg::IDE_DATA]);
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LOG_F(0, "Retrieving DATA from IDE: %x", regs[IDE_Reg::IDE_DATA]);
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return regs[IDE_Reg::IDE_DATA];
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return regs[IDE_Reg::IDE_DATA];
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@ -77,13 +68,13 @@ uint32_t AtaFullDevice::read(int reg) {
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case IDE_Reg::TIME_CONFIG:
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case IDE_Reg::TIME_CONFIG:
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return regs[IDE_Reg::TIME_CONFIG];
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return regs[IDE_Reg::TIME_CONFIG];
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default:
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default:
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LOG_F(WARNING, "Attempted to read unknown IDE register: %x", reg);
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LOG_F(WARNING, "Attempted to read unknown IDE register: %x", reg_addr);
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return 0x0;
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return 0;
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}
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}
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}
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}
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void AtaFullDevice::write(int reg, uint32_t value) {
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void AtaBaseDevice::write(const uint8_t reg_addr, const uint16_t value) {
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switch (reg) {
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switch (reg_addr) {
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case IDE_Reg::IDE_DATA:
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case IDE_Reg::IDE_DATA:
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regs[IDE_Reg::IDE_DATA] = value;
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regs[IDE_Reg::IDE_DATA] = value;
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break;
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break;
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@ -108,7 +99,7 @@ void AtaFullDevice::write(int reg, uint32_t value) {
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case IDE_Reg::COMMAND:
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case IDE_Reg::COMMAND:
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regs[IDE_Reg::COMMAND] = value;
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regs[IDE_Reg::COMMAND] = value;
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LOG_F(0, "Executing COMMAND for IDE: %x", value);
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LOG_F(0, "Executing COMMAND for IDE: %x", value);
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perform_command(value);
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perform_command();
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break;
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break;
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case IDE_Reg::DEV_CTRL:
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case IDE_Reg::DEV_CTRL:
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regs[IDE_Reg::DEV_CTRL] = value;
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regs[IDE_Reg::DEV_CTRL] = value;
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@ -117,28 +108,6 @@ void AtaFullDevice::write(int reg, uint32_t value) {
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regs[IDE_Reg::TIME_CONFIG] = value;
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regs[IDE_Reg::TIME_CONFIG] = value;
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break;
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break;
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default:
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default:
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LOG_F(WARNING, "Attempted to write unknown IDE register: %x", reg);
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LOG_F(WARNING, "Attempted to write unknown IDE register: %x", reg_addr);
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}
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}
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}
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}
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int AtaFullDevice::perform_command(uint32_t command) {
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switch (command) {
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case IDE_Cmd::READ_SECTOR:
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LOG_F(WARNING, "Trying to read sector with: %x", command);
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break;
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case IDE_Cmd::WRITE_SECTOR:
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LOG_F(WARNING, "Trying to write sector with: %x", command);
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break;
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default:
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LOG_F(WARNING, "Attempted to execute IDE command: %x", command);
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}
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return 0;
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}
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static const DeviceDescription ATA_Full_Descriptor = {
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AtaFullDevice::create, {}, {}
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};
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REGISTER_DEVICE(AtaFullDevice, ATA_Full_Descriptor);
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@ -19,32 +19,29 @@ You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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*/
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/** @file Null ATA device */
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/** @file Base class for ATA devices. */
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#include <devices/common/ata/ata_bus.h>
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#ifndef ATA_BASE_DEVICE_H
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#define ATA_BASE_DEVICE_H
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#define SEC_SIZE 512
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#include <devices/common/ata/atadefs.h>
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#include <devices/common/hwcomponent.h>
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#ifndef ATA_NULL_H
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#include <cinttypes>
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#define ATA_NULL_H
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class AtaNullDevice : public AtaBus {
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class AtaBaseDevice : public HWComponent, public AtaInterface
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{
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public:
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public:
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AtaNullDevice();
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AtaBaseDevice(const std::string name);
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~AtaNullDevice() = default;
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~AtaBaseDevice() = default;
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static std::unique_ptr<HWComponent> create() {
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uint16_t read(const uint8_t reg_addr);
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return std::unique_ptr<AtaNullDevice>(new AtaNullDevice());
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void write(const uint8_t reg_addr, const uint16_t value);
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}
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int process_command(uint32_t cmd);
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virtual int perform_command() = 0;
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uint32_t read(int reg);
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void write(int reg, uint32_t value);
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private:
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private:
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uint32_t regs[33] = {0x0};
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uint8_t regs[33] = {};
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uint8_t buffer[SEC_SIZE];
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};
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};
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#endif
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#endif // ATA_BASE_DEVICE_H
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@ -19,21 +19,12 @@ You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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*/
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/** @file ATA hard drive support */
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/** @file ATA interface definitions. */
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#ifndef IDEDEVICE_H
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#ifndef ATA_INTERFACE_H
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#define IDEDEVICE_H
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#define ATA_INTERFACE_H
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#include <devices/common/hwcomponent.h>
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#include <cinttypes>
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#include <cinttypes>
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#include <fstream>
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#include <memory>
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#include <stdio.h>
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#include <string>
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#define SEC_SIZE 512
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using namespace std;
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/** IDE register offsets. */
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/** IDE register offsets. */
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enum IDE_Reg : int {
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enum IDE_Reg : int {
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@ -92,13 +83,31 @@ enum IDE_Cmd : int {
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WRITE_DMA = 0xCA,
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WRITE_DMA = 0xCA,
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};
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};
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class AtaBus : public HWComponent {
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/** Interface for ATA devices. */
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class AtaInterface {
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public:
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public:
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AtaBus();
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AtaInterface() = default;
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~AtaBus() = default;
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virtual ~AtaInterface() = default;
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virtual uint16_t read(const uint8_t reg_addr) = 0;
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void connect_msg();
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virtual void write(const uint8_t reg_addr, const uint16_t val) = 0;
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void pass_msg();
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};
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};
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#endif
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/** Dummy ATA device. */
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class AtaNullDevice : public AtaInterface {
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public:
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AtaNullDevice() = default;
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~AtaNullDevice() = default;
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uint16_t read(const uint8_t reg_addr) {
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// return all one's except DD7 if no device is present
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// DD7 corresponds to the BSY bit of the status register
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// The host should have a pull-down resistor on DD7
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// to prevent the software from waiting for a long time
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// for empty slots
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return 0xFF7FU;
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};
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void write(const uint8_t reg_addr, const uint16_t val) {};
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};
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#endif // ATA_INTERFACE_H
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74
devices/common/ata/idechannel.cpp
Normal file
74
devices/common/ata/idechannel.cpp
Normal file
@ -0,0 +1,74 @@
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/*
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||||||
|
DingusPPC - The Experimental PowerPC Macintosh emulator
|
||||||
|
Copyright (C) 2018-22 divingkatae and maximum
|
||||||
|
(theweirdo) spatium
|
||||||
|
|
||||||
|
(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
|
||||||
|
|
||||||
|
This program is free software: you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation, either version 3 of the License, or
|
||||||
|
(at your option) any later version.
|
||||||
|
|
||||||
|
This program is distributed in the hope that it will be useful,
|
||||||
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||||
|
*/
|
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/** IDE Channel (aka IDE port) emulation.
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One IDE channel is capable of controlling up to two IDE devices.
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This class handles device registration and passing of messages
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from and to the host.
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*/
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#include <devices/common/ata/atadefs.h>
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#include <devices/common/ata/idechannel.h>
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#include <devices/common/hwcomponent.h>
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#include <devices/deviceregistry.h>
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#include <cinttypes>
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#include <memory>
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#include <string>
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IdeChannel::IdeChannel(const std::string name)
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{
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this->set_name(name);
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this->supports_types(HWCompType::IDE_BUS);
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this->devices[0] = std::unique_ptr<AtaNullDevice>(new AtaNullDevice());
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this->devices[1] = std::unique_ptr<AtaNullDevice>(new AtaNullDevice());
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}
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uint16_t IdeChannel::read(const uint8_t reg_addr, const int size)
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{
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return this->devices[this->cur_dev]->read(reg_addr);
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}
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void IdeChannel::write(const uint8_t reg_addr, const uint16_t val, const int size)
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{
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// keep track of the currently selected device
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if (reg_addr == IDE_Reg::DRIVE_HEAD) {
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this->cur_dev = (val >> 4) & 1;
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}
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// redirect register writes to both devices
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for (auto& dev : this->devices) {
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dev->write(reg_addr, val);
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}
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}
|
||||||
|
|
||||||
|
static const DeviceDescription Ide0_Descriptor = {
|
||||||
|
IdeChannel::create_first, {}, {}
|
||||||
|
};
|
||||||
|
|
||||||
|
static const DeviceDescription Ide1_Descriptor = {
|
||||||
|
IdeChannel::create_second, {}, {}
|
||||||
|
};
|
||||||
|
|
||||||
|
REGISTER_DEVICE(Ide0, Ide0_Descriptor);
|
||||||
|
REGISTER_DEVICE(Ide1, Ide1_Descriptor);
|
@ -19,37 +19,39 @@ You should have received a copy of the GNU General Public License
|
|||||||
along with this program. If not, see <https://www.gnu.org/licenses/>.
|
along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @file Full ATA device */
|
/** @file IDE Channel (aka IDE port) definitions. */
|
||||||
|
|
||||||
#include <devices/common/ata/ata_bus.h>
|
#ifndef IDE_CHANNEL_H
|
||||||
|
#define IDE_CHANNEL_H
|
||||||
|
|
||||||
#define SEC_SIZE 512
|
#include <devices/common/ata/atadefs.h>
|
||||||
|
#include <devices/common/hwcomponent.h>
|
||||||
|
|
||||||
#ifndef ATA_FULL_H
|
#include <cinttypes>
|
||||||
#define ATA_FULL_H
|
#include <memory>
|
||||||
|
#include <string>
|
||||||
|
|
||||||
class AtaFullDevice : public AtaBus {
|
class IdeChannel : public HWComponent
|
||||||
|
{
|
||||||
public:
|
public:
|
||||||
AtaFullDevice();
|
IdeChannel(const std::string name);
|
||||||
~AtaFullDevice() = default;
|
~IdeChannel() = default;
|
||||||
|
|
||||||
static std::unique_ptr<HWComponent> create() {
|
static std::unique_ptr<HWComponent> create_first() {
|
||||||
return std::unique_ptr<AtaFullDevice>(new AtaFullDevice());
|
return std::unique_ptr<IdeChannel>(new IdeChannel("IDEO"));
|
||||||
}
|
}
|
||||||
|
|
||||||
void insert_image(std::string filename);
|
static std::unique_ptr<HWComponent> create_second() {
|
||||||
uint32_t read(int reg);
|
return std::unique_ptr<IdeChannel>(new IdeChannel("IDE1"));
|
||||||
void write(int reg, uint32_t value);
|
}
|
||||||
|
|
||||||
int perform_command(uint32_t command);
|
uint16_t read(const uint8_t reg_addr, const int size);
|
||||||
void get_status();
|
void write(const uint8_t reg_addr, const uint16_t val, const int size);
|
||||||
|
|
||||||
private:
|
private:
|
||||||
uint32_t regs[33] = {0x0};
|
int cur_dev = 0;
|
||||||
uint8_t buffer[SEC_SIZE];
|
|
||||||
std::fstream ide_img;
|
std::unique_ptr<AtaInterface> devices[2];
|
||||||
uint64_t img_size;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#endif // IDE_CHANNEL_H
|
||||||
#endif
|
|
@ -21,11 +21,10 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
|
|||||||
|
|
||||||
#include <cpu/ppc/ppcemu.h>
|
#include <cpu/ppc/ppcemu.h>
|
||||||
#include <devices/deviceregistry.h>
|
#include <devices/deviceregistry.h>
|
||||||
|
#include <devices/common/ata/idechannel.h>
|
||||||
#include <devices/common/dbdma.h>
|
#include <devices/common/dbdma.h>
|
||||||
#include <devices/common/hwcomponent.h>
|
#include <devices/common/hwcomponent.h>
|
||||||
#include <devices/common/viacuda.h>
|
#include <devices/common/viacuda.h>
|
||||||
#include <devices/common/ata/ata_full.h>
|
|
||||||
#include <devices/common/ata/ata_null.h>
|
|
||||||
#include <devices/floppy/swim3.h>
|
#include <devices/floppy/swim3.h>
|
||||||
#include <devices/ioctrl/macio.h>
|
#include <devices/ioctrl/macio.h>
|
||||||
#include <devices/serial/escc.h>
|
#include <devices/serial/escc.h>
|
||||||
@ -81,13 +80,8 @@ HeathrowIC::HeathrowIC() : PCIDevice("mac-io/heathrow"), InterruptCtrl()
|
|||||||
this->mesh = dynamic_cast<MESHController*>(gMachineObj->get_comp_by_name("Mesh"));
|
this->mesh = dynamic_cast<MESHController*>(gMachineObj->get_comp_by_name("Mesh"));
|
||||||
|
|
||||||
// connect IDE HW
|
// connect IDE HW
|
||||||
this->ide_0 = dynamic_cast<AtaNullDevice*>(gMachineObj->get_comp_by_name("AtaNullDevice"));
|
this->ide_0 = dynamic_cast<IdeChannel*>(gMachineObj->get_comp_by_name("Ide0"));
|
||||||
this->ide_1 = dynamic_cast<AtaNullDevice*>(gMachineObj->get_comp_by_name("AtaNullDevice"));
|
this->ide_1 = dynamic_cast<IdeChannel*>(gMachineObj->get_comp_by_name("Ide1"));
|
||||||
|
|
||||||
//std::string hd_image_path = GET_STR_PROP("hdd_img");
|
|
||||||
//if (!hd_image_path.empty()) {
|
|
||||||
// this->ide_1->insert_image(hd_image_path);
|
|
||||||
//}
|
|
||||||
|
|
||||||
// connect serial HW
|
// connect serial HW
|
||||||
this->escc = dynamic_cast<EsccController*>(gMachineObj->get_comp_by_name("Escc"));
|
this->escc = dynamic_cast<EsccController*>(gMachineObj->get_comp_by_name("Escc"));
|
||||||
@ -168,17 +162,15 @@ uint32_t HeathrowIC::read(uint32_t rgn_start, uint32_t offset, int size) {
|
|||||||
break;
|
break;
|
||||||
case 0x15: // SWIM3
|
case 0x15: // SWIM3
|
||||||
return this->swim3->read((offset >> 4 )& 0xF);
|
return this->swim3->read((offset >> 4 )& 0xF);
|
||||||
case 0x16:
|
case 0x16: // VIA-CUDA
|
||||||
case 0x17:
|
case 0x17:
|
||||||
res = this->viacuda->read((offset - 0x16000) >> 9);
|
res = this->viacuda->read((offset - 0x16000) >> 9);
|
||||||
break;
|
break;
|
||||||
case 0x20: // IDE 0
|
case 0x20: // IDE 0
|
||||||
LOG_F(0, "Read IDE 0 - offset=0x%X", offset);
|
res = this->ide_0->read((offset >> 4) & 0x1F, size);
|
||||||
res = this->ide_0->read((offset >> 4) & 0x1F);
|
|
||||||
break;
|
break;
|
||||||
case 0x21: // IDE 1
|
case 0x21: // IDE 1
|
||||||
LOG_F(0, "Read IDE 1 - offset=0x%X", offset);
|
res = this->ide_1->read((offset >> 4) & 0x1F, size);
|
||||||
res = this->ide_1->read((offset >> 4) & 0x1F);
|
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
if (sub_addr >= 0x60) {
|
if (sub_addr >= 0x60) {
|
||||||
@ -221,17 +213,15 @@ void HeathrowIC::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int
|
|||||||
case 0x15: // SWIM3
|
case 0x15: // SWIM3
|
||||||
this->swim3->write((offset >> 4) & 0xF, value);
|
this->swim3->write((offset >> 4) & 0xF, value);
|
||||||
break;
|
break;
|
||||||
case 0x16:
|
case 0x16: // VIA-CUDA
|
||||||
case 0x17:
|
case 0x17:
|
||||||
this->viacuda->write((offset - 0x16000) >> 9, value);
|
this->viacuda->write((offset - 0x16000) >> 9, value);
|
||||||
break;
|
break;
|
||||||
case 0x20:
|
case 0x20: // IDE O
|
||||||
LOG_F(0, "Write IDE 0 - offset=0x%X", offset);
|
this->ide_0->write((offset >> 4) & 0x1F, value, size);
|
||||||
this->ide_0->write((offset >> 4) & 0x1F, value);
|
|
||||||
break;
|
break;
|
||||||
case 0x21:
|
case 0x21: // IDE 1
|
||||||
LOG_F(0, "Write IDE 1 - offset=0x%X", offset);
|
this->ide_1->write((offset >> 4) & 0x1F, value, size);
|
||||||
this->ide_1->write((offset >> 4) & 0x1F, value);
|
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
if (sub_addr >= 0x60) {
|
if (sub_addr >= 0x60) {
|
||||||
@ -409,7 +399,7 @@ void HeathrowIC::clear_cpu_int()
|
|||||||
}
|
}
|
||||||
|
|
||||||
static const vector<string> Heathrow_Subdevices = {
|
static const vector<string> Heathrow_Subdevices = {
|
||||||
"NVRAM", "ViaCuda", "Mesh", "Escc", "Swim3", "AtaNullDevice"};
|
"NVRAM", "ViaCuda", "Mesh", "Escc", "Swim3", "Ide0", "Ide1"};
|
||||||
|
|
||||||
static const DeviceDescription Heathrow_Descriptor = {
|
static const DeviceDescription Heathrow_Descriptor = {
|
||||||
HeathrowIC::create, Heathrow_Subdevices, {}
|
HeathrowIC::create, Heathrow_Subdevices, {}
|
||||||
|
@ -51,11 +51,10 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
|
|||||||
#ifndef MACIO_H
|
#ifndef MACIO_H
|
||||||
#define MACIO_H
|
#define MACIO_H
|
||||||
|
|
||||||
|
#include <devices/common/ata/idechannel.h>
|
||||||
#include <devices/common/dbdma.h>
|
#include <devices/common/dbdma.h>
|
||||||
#include <devices/common/mmiodevice.h>
|
#include <devices/common/mmiodevice.h>
|
||||||
#include <devices/common/nvram.h>
|
#include <devices/common/nvram.h>
|
||||||
#include <devices/common/ata/ata_full.h>
|
|
||||||
#include <devices/common/ata/ata_null.h>
|
|
||||||
#include <devices/common/pci/pcidevice.h>
|
#include <devices/common/pci/pcidevice.h>
|
||||||
#include <devices/common/pci/pcihost.h>
|
#include <devices/common/pci/pcihost.h>
|
||||||
#include <devices/common/scsi/mesh.h>
|
#include <devices/common/scsi/mesh.h>
|
||||||
@ -139,8 +138,6 @@ private:
|
|||||||
MaceController* mace;
|
MaceController* mace;
|
||||||
ViaCuda* viacuda; // VIA cell with Cuda MCU attached to it
|
ViaCuda* viacuda; // VIA cell with Cuda MCU attached to it
|
||||||
EsccController* escc; // ESCC serial controller
|
EsccController* escc; // ESCC serial controller
|
||||||
AtaNullDevice* ide_0; // Internal ATA
|
|
||||||
AtaNullDevice* ide_1; // Media Bay ATA
|
|
||||||
Sc53C94* scsi_0; // external SCSI
|
Sc53C94* scsi_0; // external SCSI
|
||||||
Swim3::Swim3Ctrl* swim3; // floppy disk controller
|
Swim3::Swim3Ctrl* swim3; // floppy disk controller
|
||||||
|
|
||||||
@ -233,8 +230,8 @@ private:
|
|||||||
ViaCuda* viacuda; // VIA cell with Cuda MCU attached to it
|
ViaCuda* viacuda; // VIA cell with Cuda MCU attached to it
|
||||||
MESHController* mesh; // MESH SCSI cell instance
|
MESHController* mesh; // MESH SCSI cell instance
|
||||||
EsccController* escc; // ESCC serial controller
|
EsccController* escc; // ESCC serial controller
|
||||||
AtaNullDevice* ide_0; // Internal ATA
|
IdeChannel* ide_0; // Internal ATA
|
||||||
AtaNullDevice* ide_1; // Media Bay ATA
|
IdeChannel* ide_1; // Media Bay ATA
|
||||||
Swim3::Swim3Ctrl* swim3; // floppy disk controller
|
Swim3::Swim3Ctrl* swim3; // floppy disk controller
|
||||||
|
|
||||||
std::unique_ptr<DMAChannel> snd_out_dma;
|
std::unique_ptr<DMAChannel> snd_out_dma;
|
||||||
|
Loading…
x
Reference in New Issue
Block a user