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Adding further Heathrow registers

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dingusdev 2020-04-19 11:28:51 -07:00
parent 8fb2e851d7
commit add11ecc62
2 changed files with 36 additions and 0 deletions
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32
devices/heathrow.cpp
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@ -182,6 +182,18 @@ uint32_t HeathrowIC::mio_ctrl_read(uint32_t offset, int size)
uint32_t res = 0;
switch (offset & 0xFF) {
case 0x14:
LOG_F(9, "read from MIO:Int_Mask2 register \n");
res = this->int_mask2;
break;
case 0x18:
LOG_F(9, "read from MIO:Int_Clear2 register \n");
res = this->int_clear2;
break;
case 0x1C:
LOG_F(9, "read from MIO:Int_Levels2 register \n");
res = this->int_levels2;
break;
case 0x24:
LOG_F(9, "read from MIO:Int_Mask1 register \n");
res = this->int_mask1;
@ -190,6 +202,10 @@ uint32_t HeathrowIC::mio_ctrl_read(uint32_t offset, int size)
LOG_F(9, "read from MIO:Int_Clear1 register \n");
res = this->int_clear1;
break;
case 0x2C:
LOG_F(9, "read from MIO:Int_Levels1 register \n");
res = this->int_levels1;
break;
case 0x34: /* heathrowIDs / HEATHROW_MBCR (Linux): media bay config reg? */
res = 0xF0700000UL;
break;
@ -208,6 +224,18 @@ uint32_t HeathrowIC::mio_ctrl_read(uint32_t offset, int size)
void HeathrowIC::mio_ctrl_write(uint32_t offset, uint32_t value, int size)
{
switch (offset & 0xFF) {
case 0x14:
LOG_F(9, "read from MIO:Int_Mask2 register \n");
this->int_mask2 = value;
break;
case 0x18:
LOG_F(9, "read from MIO:Int_Clear2 register \n");
this->int_clear2 = value;
break;
case 0x1C:
LOG_F(9, "read from MIO:Int_Levels2 register \n");
this->int_levels2 = value;
break;
case 0x24:
LOG_F(9, "write %x to MIO:Int_Mask1 register \n", value);
this->int_mask1 = value;
@ -216,6 +244,10 @@ void HeathrowIC::mio_ctrl_write(uint32_t offset, uint32_t value, int size)
LOG_F(9, "write %x to MIO:Int_Clear1 register \n", value);
this->int_clear1 = value;
break;
case 0x2C:
LOG_F(9, "read from MIO:Int_Levels1 register \n");
this->int_levels1 = value;
break;
case 0x38:
LOG_F(9, "write %x to MIO:Feat_Ctrl register \n", value);
this->feat_ctrl = value;

4
devices/macio.h
View File

@ -126,8 +126,12 @@ private:
0x00, 0x00 // unknown defaults
};
uint32_t int_mask2;
uint32_t int_clear2;
uint32_t int_levels2;
uint32_t int_mask1;
uint32_t int_clear1;
uint32_t int_levels1;
uint32_t feat_ctrl; // features control register
/* device cells */