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ppcfpopcodes: improve mffs, mtfsb0 and mtfsb1.
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@ -845,9 +845,8 @@ void dppc_interpreter::ppc_fmr() {
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void dppc_interpreter::ppc_mffs() {
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ppc_grab_regsda();
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uint64_t fpstore1 = ppc_state.fpr[reg_d].int64_r & ((uint64_t)0xFFF80000 << 32);
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fpstore1 |= (uint64_t)ppc_state.fpscr;
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fp_save_uint64(fpstore1);
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ppc_state.fpr[reg_d].int64_r = (uint64_t)ppc_state.fpscr;
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if (rc_flag)
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ppc_update_cr1();
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@ -884,8 +883,8 @@ void dppc_interpreter::ppc_mtfsfi() {
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}
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void dppc_interpreter::ppc_mtfsb0() {
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crf_d = (ppc_cur_instruction >> 21) & 0x1F;
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if ((crf_d == 0) || (crf_d > 2)) {
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int crf_d = (ppc_cur_instruction >> 21) & 0x1F;
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if (!crf_d || (crf_d > 2)) { // FEX and VX can't be explicitely cleared
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ppc_state.fpscr &= ~(0x80000000UL >> crf_d);
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}
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@ -894,8 +893,8 @@ void dppc_interpreter::ppc_mtfsb0() {
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}
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void dppc_interpreter::ppc_mtfsb1() {
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crf_d = (ppc_cur_instruction >> 21) & 0x1F;
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if ((crf_d == 0) || (crf_d > 2)) {
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int crf_d = (ppc_cur_instruction >> 21) & 0x1F;
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if (!crf_d || (crf_d > 2)) { // FEX and VX can't be explicitely set
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ppc_state.fpscr |= (0x80000000UL >> crf_d);
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}
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