From b60d3061b767b797fa0d178201a9945be6f51f07 Mon Sep 17 00:00:00 2001 From: joevt Date: Fri, 26 Apr 2024 20:14:19 -0700 Subject: [PATCH] escc: WR9 fixes. Update write_regs[WR9] even though most or all of the bits are in master_int_cntrl. Fix hardware reset for WR9. It's supposed to leave WR9_NO_VECTOR | WR9_VECTOR_INCLUDES_STATUS unchanged. Fix channel reset for WR9. It's supposed to clear WR9_INTERRUPT_MASKING_WITHOUT_INTACK. --- devices/serial/escc.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/devices/serial/escc.cpp b/devices/serial/escc.cpp index fddad9f..462b2c8 100644 --- a/devices/serial/escc.cpp +++ b/devices/serial/escc.cpp @@ -66,7 +66,7 @@ EsccController::EsccController() void EsccController::reset() { - this->master_int_cntrl &= ~(WR9_NO_VECTOR | WR9_VECTOR_INCLUDES_STATUS); + this->master_int_cntrl &= (WR9_NO_VECTOR | WR9_VECTOR_INCLUDES_STATUS); this->master_int_cntrl |= WR9_FORCE_HARDWARE_RESET; this->reg_ptr = WR0; // or RR0 @@ -240,10 +240,13 @@ void EsccChannel::reset(bool hw_reset) this->brg_clock_src = 0; if (hw_reset) { + this->write_regs[WR9] &= 0x03; // clear all except (WR9_NO_VECTOR | WR9_VECTOR_INCLUDES_STATUS) + this->write_regs[WR9] |= 0xC0; // set WR9_FORCE_HARDWARE_RESET this->write_regs[WR10] = 0; this->write_regs[WR11] = 8; this->write_regs[WR14] &= 0xC0; } else { + this->write_regs[WR9] &= ~0x20; // clear WR9_INTERRUPT_MASKING_WITHOUT_INTACK this->write_regs[WR10] &= 0x60; this->write_regs[WR14] &= 0xC3; }