mirror of
https://github.com/dingusdev/dingusppc.git
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ppcmmu: replace macros with function templates.
This commit is contained in:
Maxim Poliakovski
parent
ed6c316c82
commit
bc59bf7c43
@ -55,57 +55,112 @@ AddressMapEntry last_ptab_area = {0xFFFFFFFF, 0xFFFFFFFF};
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AddressMapEntry last_dma_area = {0xFFFFFFFF, 0xFFFFFFFF};
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#define WRITE_BYTE(addr, val) (*(addr) = val)
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/* macro for generating code reading from physical memory */
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#define READ_PHYS_MEM(ENTRY, ADDR, OP, SIZE, UNVAL) \
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{ \
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if ((ADDR) >= (ENTRY).start && ((ADDR) + (SIZE)) <= (ENTRY).end) { \
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ret = OP((ENTRY).mem_ptr + ((ADDR) - (ENTRY).start)); \
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} else { \
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AddressMapEntry* entry = mem_ctrl_instance->find_range((ADDR)); \
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if (entry) { \
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if (entry->type & (RT_ROM | RT_RAM)) { \
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(ENTRY).start = entry->start; \
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(ENTRY).end = entry->end; \
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(ENTRY).mem_ptr = entry->mem_ptr; \
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ret = OP((ENTRY).mem_ptr + ((ADDR) - (ENTRY).start)); \
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} else if (entry->type & RT_MMIO) { \
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ret = entry->devobj->read(entry->start, (ADDR)-entry->start, (SIZE)); \
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} else { \
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LOG_F(ERROR, "Please check your address map! \n"); \
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ret = (UNVAL); \
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} \
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} else { \
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LOG_F(WARNING, "Read from unmapped memory at 0x%08X!\n", (ADDR)); \
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ret = (UNVAL); \
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} \
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} \
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template <class T, const bool is_aligned>
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static inline T read_phys_mem(AddressMapEntry *mru_rgn, uint32_t addr)
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{
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if (addr < mru_rgn->start || (addr + sizeof(T)) > mru_rgn->end) {
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AddressMapEntry* entry = mem_ctrl_instance->find_range(addr);
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if (entry) {
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*mru_rgn = *entry;
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} else {
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LOG_F(ERROR, "Read from unmapped memory at 0x%08X!\n", addr);
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return (-1ULL ? sizeof(T) == 8 : -1UL);
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}
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}
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/* macro for generating code writing to physical memory */
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#define WRITE_PHYS_MEM(ENTRY, ADDR, OP, VAL, SIZE) \
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{ \
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if ((ADDR) >= (ENTRY).start && ((ADDR) + (SIZE)) <= (ENTRY).end) { \
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OP((ENTRY).mem_ptr + ((ADDR) - (ENTRY).start), (VAL)); \
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} else { \
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AddressMapEntry* entry = mem_ctrl_instance->find_range((ADDR)); \
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if (entry) { \
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if (entry->type & RT_RAM) { \
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(ENTRY).start = entry->start; \
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(ENTRY).end = entry->end; \
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(ENTRY).mem_ptr = entry->mem_ptr; \
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OP((ENTRY).mem_ptr + ((ADDR) - (ENTRY).start), (VAL)); \
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} else if (entry->type & RT_MMIO) { \
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entry->devobj->write(entry->start, (ADDR)-entry->start, (VAL), (SIZE)); \
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} else { \
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LOG_F(ERROR, "Please check your address map!\n"); \
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} \
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} else { \
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LOG_F(WARNING, "Write to unmapped memory at 0x%08X!\n", (ADDR)); \
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} \
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} \
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if (mru_rgn->type & (RT_ROM | RT_RAM)) {
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#ifdef MMU_PROFILING
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dmem_reads_total++;
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#endif
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switch(sizeof(T)) {
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case 1:
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return *(mru_rgn->mem_ptr + (addr - mru_rgn->start));
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case 2:
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if (is_aligned) {
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return READ_WORD_BE_A(mru_rgn->mem_ptr + (addr - mru_rgn->start));
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} else {
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return READ_WORD_BE_U(mru_rgn->mem_ptr + (addr - mru_rgn->start));
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}
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case 4:
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if (is_aligned) {
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return READ_DWORD_BE_A(mru_rgn->mem_ptr + (addr - mru_rgn->start));
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} else {
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return READ_DWORD_BE_U(mru_rgn->mem_ptr + (addr - mru_rgn->start));
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}
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case 8:
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if (is_aligned) {
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return READ_QWORD_BE_A(mru_rgn->mem_ptr + (addr - mru_rgn->start));
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}
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default:
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LOG_F(ERROR, "READ_PHYS: invalid size %lu passed\n", sizeof(T));
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return (-1ULL ? sizeof(T) == 8 : -1UL);
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}
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} else if (mru_rgn->type & RT_MMIO) {
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#ifdef MMU_PROFILING
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iomem_reads_total++;
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#endif
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return (mru_rgn->devobj->read(mru_rgn->start,
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addr - mru_rgn->start, sizeof(T)));
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} else {
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LOG_F(ERROR, "READ_PHYS: invalid region type!\n");
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return (-1ULL ? sizeof(T) == 8 : -1UL);
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}
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}
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template <class T, const bool is_aligned>
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static inline void write_phys_mem(AddressMapEntry *mru_rgn, uint32_t addr, T value)
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{
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if (addr < mru_rgn->start || (addr + sizeof(T)) > mru_rgn->end) {
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AddressMapEntry* entry = mem_ctrl_instance->find_range(addr);
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if (entry) {
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*mru_rgn = *entry;
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} else {
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LOG_F(ERROR, "Write to unmapped memory at 0x%08X!\n", addr);
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return;
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}
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}
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if (mru_rgn->type & RT_RAM) {
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#ifdef MMU_PROFILING
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dmem_writes_total++;
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#endif
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switch(sizeof(T)) {
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case 1:
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*(mru_rgn->mem_ptr + (addr - mru_rgn->start)) = value;
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break;
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case 2:
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if (is_aligned) {
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WRITE_WORD_BE_A(mru_rgn->mem_ptr + (addr - mru_rgn->start), value);
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} else {
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WRITE_WORD_BE_U(mru_rgn->mem_ptr + (addr - mru_rgn->start), value);
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}
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break;
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case 4:
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if (is_aligned) {
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WRITE_DWORD_BE_A(mru_rgn->mem_ptr + (addr - mru_rgn->start), value);
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} else {
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WRITE_DWORD_BE_U(mru_rgn->mem_ptr + (addr - mru_rgn->start), value);
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}
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break;
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case 8:
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if (is_aligned) {
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WRITE_QWORD_BE_A(mru_rgn->mem_ptr + (addr - mru_rgn->start), value);
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}
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break;
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default:
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LOG_F(ERROR, "WRITE_PHYS: invalid size %lu passed\n", sizeof(T));
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return;
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}
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} else if (mru_rgn->type & RT_MMIO) {
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#ifdef MMU_PROFILING
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iomem_writes_total++;
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#endif
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mru_rgn->devobj->write(mru_rgn->start, addr - mru_rgn->start, value,
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sizeof(T));
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} else {
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LOG_F(ERROR, "WRITE_PHYS: invalid region type!\n");
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}
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}
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uint8_t* mmu_get_dma_mem(uint32_t addr, uint32_t size) {
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if (addr >= last_dma_area.start && (addr + size) <= last_dma_area.end) {
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@ -385,28 +440,28 @@ static void mem_write_unaligned(uint32_t addr, uint32_t value, uint32_t size) {
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uint32_t phys_addr;
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uint32_t shift = (size - 1) * 8;
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// Break misaligned memory accesses into multiple, smaller accesses
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// Break misaligned memory accesses into multiple, bytewise accesses
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// and retranslate on page boundary.
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// Because such accesses suffer a performance penalty, they will be
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// presumably very rare so don't care much about performance.
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for (int i = 0; i < size; shift -= 8, addr++, phys_addr++, i++) {
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if ((ppc_state.msr & 0x10) && (!i || !(addr & 0xFFF))) {
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phys_addr = ppc_mmu_addr_translate(addr, 0);
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phys_addr = ppc_mmu_addr_translate(addr, 1);
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}
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WRITE_PHYS_MEM(last_write_area, phys_addr, WRITE_BYTE,
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(value >> shift) & 0xFF, 1);
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write_phys_mem<uint8_t, false>(&last_write_area, phys_addr,
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(value >> shift) & 0xFF);
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}
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} else {
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// data address translation if enabled
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if (ppc_state.msr & 0x10) {
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addr = ppc_mmu_addr_translate(addr, 0);
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addr = ppc_mmu_addr_translate(addr, 1);
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}
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if (size == 2) {
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WRITE_PHYS_MEM(last_write_area, addr, WRITE_WORD_BE_U, value, 2);
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write_phys_mem<uint16_t, false>(&last_write_area, addr, value);
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} else {
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WRITE_PHYS_MEM(last_write_area, addr, WRITE_DWORD_BE_U, value, 4);
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write_phys_mem<uint32_t, false>(&last_write_area, addr, value);
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}
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}
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}
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@ -417,12 +472,13 @@ void mem_write_byte(uint32_t addr, uint8_t value) {
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addr = ppc_mmu_addr_translate(addr, 1);
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}
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WRITE_PHYS_MEM(last_write_area, addr, WRITE_BYTE, value, 1);
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write_phys_mem<uint8_t, true>(&last_write_area, addr, value);
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}
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void mem_write_word(uint32_t addr, uint16_t value) {
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if (addr & 1) {
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mem_write_unaligned(addr, value, 2);
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return;
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}
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/* data address translation if enabled */
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@ -430,12 +486,13 @@ void mem_write_word(uint32_t addr, uint16_t value) {
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addr = ppc_mmu_addr_translate(addr, 1);
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}
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WRITE_PHYS_MEM(last_write_area, addr, WRITE_WORD_BE_A, value, 2);
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write_phys_mem<uint16_t, true>(&last_write_area, addr, value);
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}
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void mem_write_dword(uint32_t addr, uint32_t value) {
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if (addr & 3) {
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mem_write_unaligned(addr, value, 4);
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return;
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}
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/* data address translation if enabled */
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@ -443,7 +500,7 @@ void mem_write_dword(uint32_t addr, uint32_t value) {
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addr = ppc_mmu_addr_translate(addr, 1);
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}
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WRITE_PHYS_MEM(last_write_area, addr, WRITE_DWORD_BE_A, value, 4);
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write_phys_mem<uint32_t, true>(&last_write_area, addr, value);
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}
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void mem_write_qword(uint32_t addr, uint64_t value) {
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@ -457,7 +514,7 @@ void mem_write_qword(uint32_t addr, uint64_t value) {
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addr = ppc_mmu_addr_translate(addr, 1);
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}
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WRITE_PHYS_MEM(last_write_area, addr, WRITE_QWORD_BE_A, value, 8);
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write_phys_mem<uint64_t, true>(&last_write_area, addr, value);
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}
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static uint32_t mem_grab_unaligned(uint32_t addr, uint32_t size) {
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@ -475,7 +532,7 @@ static uint32_t mem_grab_unaligned(uint32_t addr, uint32_t size) {
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uint32_t phys_addr;
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uint32_t res = 0;
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// Break misaligned memory accesses into multiple, smaller accesses
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// Break misaligned memory accesses into multiple, bytewise accesses
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// and retranslate on page boundary.
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// Because such accesses suffer a performance penalty, they will be
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// presumably very rare so don't care much about performance.
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@ -484,8 +541,7 @@ static uint32_t mem_grab_unaligned(uint32_t addr, uint32_t size) {
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phys_addr = ppc_mmu_addr_translate(addr, 0);
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}
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READ_PHYS_MEM(last_read_area, phys_addr, *, 1, 0xFFU);
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res = (res << 8) | ret;
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res = (res << 8) | read_phys_mem<uint8_t, false>(&last_read_area, phys_addr);
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}
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return res;
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@ -496,9 +552,9 @@ static uint32_t mem_grab_unaligned(uint32_t addr, uint32_t size) {
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}
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if (size == 2) {
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READ_PHYS_MEM(last_read_area, addr, READ_WORD_BE_U, 2, 0xFFFFU);
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return read_phys_mem<uint16_t, false>(&last_read_area, addr);
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} else {
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READ_PHYS_MEM(last_read_area, addr, READ_DWORD_BE_U, 4, 0xFFFFFFFFUL);
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return read_phys_mem<uint32_t, false>(&last_read_area, addr);
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}
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}
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@ -507,20 +563,15 @@ static uint32_t mem_grab_unaligned(uint32_t addr, uint32_t size) {
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/** Grab a value from memory into a register */
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uint8_t mem_grab_byte(uint32_t addr) {
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uint8_t ret;
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/* data address translation if enabled */
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if (ppc_state.msr & 0x10) {
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addr = ppc_mmu_addr_translate(addr, 0);
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}
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READ_PHYS_MEM(last_read_area, addr, *, 1, 0xFFU);
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return ret;
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return read_phys_mem<uint8_t, true>(&last_read_area, addr);
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}
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uint16_t mem_grab_word(uint32_t addr) {
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uint16_t ret;
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if (addr & 1) {
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return mem_grab_unaligned(addr, 2);
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}
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@ -530,13 +581,10 @@ uint16_t mem_grab_word(uint32_t addr) {
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addr = ppc_mmu_addr_translate(addr, 0);
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}
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READ_PHYS_MEM(last_read_area, addr, READ_WORD_BE_A, 2, 0xFFFFU);
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return ret;
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return read_phys_mem<uint16_t, true>(&last_read_area, addr);
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}
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uint32_t mem_grab_dword(uint32_t addr) {
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uint32_t ret;
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if (addr & 3) {
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return mem_grab_unaligned(addr, 4);
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}
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@ -546,13 +594,10 @@ uint32_t mem_grab_dword(uint32_t addr) {
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addr = ppc_mmu_addr_translate(addr, 0);
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}
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READ_PHYS_MEM(last_read_area, addr, READ_DWORD_BE_A, 4, 0xFFFFFFFFUL);
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return ret;
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return read_phys_mem<uint32_t, true>(&last_read_area, addr);
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}
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uint64_t mem_grab_qword(uint32_t addr) {
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uint64_t ret;
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if (addr & 7) {
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LOG_F(ERROR, "SOS! Attempt to read unaligned QWORD at 0x%08X\n", addr);
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exit(-1); // FIXME!
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@ -563,8 +608,7 @@ uint64_t mem_grab_qword(uint32_t addr) {
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addr = ppc_mmu_addr_translate(addr, 0);
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}
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READ_PHYS_MEM(last_read_area, addr, READ_QWORD_BE_A, 8, 0xFFFFFFFFFFFFFFFFULL);
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return ret;
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return read_phys_mem<uint64_t, true>(&last_read_area, addr);
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}
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uint8_t* quickinstruction_translate(uint32_t addr) {
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