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heathrow: fix processing of emulated interrupts.

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This commit is contained in:
Maxim Poliakovski 2023-09-25 02:05:57 +02:00
parent 4cdb81e822
commit c115a887d8
1 changed files with 26 additions and 17 deletions
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29
devices/ioctrl/heathrow.cpp
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@ -315,12 +315,8 @@ void HeathrowIC::mio_ctrl_write(uint32_t offset, uint32_t value, int size) {
this->int_mask2 |= BYTESWAP_32(value) & ~MACIO_INT_MODE; this->int_mask2 |= BYTESWAP_32(value) & ~MACIO_INT_MODE;
break; break;
case MIO_INT_CLEAR2: case MIO_INT_CLEAR2:
if (value & MACIO_INT_CLR) { this->int_events2 &= ~(BYTESWAP_32(value) & 0x7FFFFFFFUL);
this->int_events2 = 0;
clear_cpu_int(); clear_cpu_int();
} else {
this->int_events2 &= BYTESWAP_32(value);
}
break; break;
case MIO_INT_MASK1: case MIO_INT_MASK1:
this->int_mask1 = BYTESWAP_32(value); this->int_mask1 = BYTESWAP_32(value);
@ -328,12 +324,13 @@ void HeathrowIC::mio_ctrl_write(uint32_t offset, uint32_t value, int size) {
this->int_mask2 = (this->int_mask2 & ~MACIO_INT_MODE) | (this->int_mask1 & MACIO_INT_MODE); this->int_mask2 = (this->int_mask2 & ~MACIO_INT_MODE) | (this->int_mask1 & MACIO_INT_MODE);
break; break;
case MIO_INT_CLEAR1: case MIO_INT_CLEAR1:
if (value & MACIO_INT_CLR) { if ((this->int_mask1 & MACIO_INT_MODE) && (value & MACIO_INT_CLR)) {
this->int_events1 = 0; this->int_events1 = 0;
clear_cpu_int(); this->int_events2 = 0;
} else { } else {
this->int_events1 &= BYTESWAP_32(value); this->int_events1 &= ~(BYTESWAP_32(value) & 0x7FFFFFFFUL);
} }
clear_cpu_int();
break; break;
case MIO_OHARE_ID: case MIO_OHARE_ID:
LOG_F(WARNING, "Attempted to write %x to MIO:ID at %x; Address : %x", value, offset, ppc_state.pc); LOG_F(WARNING, "Attempted to write %x to MIO:ID at %x; Address : %x", value, offset, ppc_state.pc);
@ -391,8 +388,8 @@ uint32_t HeathrowIC::register_dma_int(IntSrc src_id)
void HeathrowIC::ack_int(uint32_t irq_id, uint8_t irq_line_state) void HeathrowIC::ack_int(uint32_t irq_id, uint8_t irq_line_state)
{ {
if (this->int_mask1 & MACIO_INT_MODE) { // 68k interrupt emulation mode? if (this->int_mask1 & MACIO_INT_MODE) { // 68k interrupt emulation mode?
if (irq_id > 0x200000) { if (irq_id >= (1 << 20)) { // irq_id in the range of int_events2?
irq_id >>= 21; irq_id >>= (20 - 10); // adjust for non-DMA interrupt bits of int_events2
this->int_events2 |= irq_id; // signal IRQ line change this->int_events2 |= irq_id; // signal IRQ line change
this->int_events2 &= this->int_mask2; this->int_events2 &= this->int_mask2;
// update IRQ line state // update IRQ line state
@ -421,6 +418,17 @@ void HeathrowIC::ack_int(uint32_t irq_id, uint8_t irq_line_state)
void HeathrowIC::ack_dma_int(uint32_t irq_id, uint8_t irq_line_state) void HeathrowIC::ack_dma_int(uint32_t irq_id, uint8_t irq_line_state)
{ {
if (this->int_mask1 & MACIO_INT_MODE) { // 68k interrupt emulation mode? if (this->int_mask1 & MACIO_INT_MODE) { // 68k interrupt emulation mode?
if (irq_id >= (1 << 10)) { // irq_id in the range of int_events2?
irq_id >>= 10; // adjust for DMA interrupt bits of int_events2
this->int_events2 |= irq_id; // signal IRQ line change
this->int_events2 &= this->int_mask2;
// update IRQ line state
if (irq_line_state) {
this->int_levels2 |= irq_id;
} else {
this->int_levels2 &= ~irq_id;
}
} else {
this->int_events1 |= irq_id; // signal IRQ line change this->int_events1 |= irq_id; // signal IRQ line change
this->int_events1 &= this->int_mask1; this->int_events1 &= this->int_mask1;
// update IRQ line state // update IRQ line state
@ -429,6 +437,7 @@ void HeathrowIC::ack_dma_int(uint32_t irq_id, uint8_t irq_line_state)
} else { } else {
this->int_levels1 &= ~irq_id; this->int_levels1 &= ~irq_id;
} }
}
this->signal_cpu_int(); this->signal_cpu_int();
} else { } else {
ABORT_F("%s: native interrupt mode not implemented", this->name.c_str()); ABORT_F("%s: native interrupt mode not implemented", this->name.c_str());