From c2a63bab0923c20ae2e68ab40e16fbad6df025c7 Mon Sep 17 00:00:00 2001 From: dingusdev Date: Sat, 30 Oct 2021 16:43:13 -0700 Subject: [PATCH] FP Opcode Test Fixes --- cpu/ppc/ppcemu.h | 11 +- cpu/ppc/ppcfpopcodes.cpp | 235 ++++++----- cpu/ppc/test/genppctests.py | 14 +- cpu/ppc/test/ppcfloattests.csv | 728 ++++++++++++++++----------------- cpu/ppc/test/ppctests.cpp | 7 +- 5 files changed, 507 insertions(+), 488 deletions(-) diff --git a/cpu/ppc/ppcemu.h b/cpu/ppc/ppcemu.h index 2ba733f..607a2e4 100644 --- a/cpu/ppc/ppcemu.h +++ b/cpu/ppc/ppcemu.h @@ -206,12 +206,11 @@ enum CR_select : int32_t { CR1_field = (0xF << 24), }; -enum CRx_bit : uint32_t { - CR_SO = 0, - CR_EQ, - CR_GT, - CR_LT -}; +enum CRx_bit : uint32_t { + CR_SO = 28, + CR_EQ = 29, + CR_GT = 30, + CR_LT = 31 }; enum CR1_bit : uint32_t { CR1_OX = 24, diff --git a/cpu/ppc/ppcfpopcodes.cpp b/cpu/ppc/ppcfpopcodes.cpp index dd5f874..47331bb 100644 --- a/cpu/ppc/ppcfpopcodes.cpp +++ b/cpu/ppc/ppcfpopcodes.cpp @@ -19,7 +19,7 @@ You should have received a copy of the GNU General Public License along with this program. If not, see . */ -// The opcodes for the processor - ppcopcodes.cpp +// The floating point opcodes for the processor - ppcfpopcodes.cpp #include "ppcemu.h" #include "ppcmmu.h" @@ -236,72 +236,79 @@ void ppc_confirm_inf_nan(int chosen_reg_1, int chosen_reg_2, int chosen_reg_3, b } } +template void fpresult_update(double set_result, bool confirm_arc) { - bool confirm_ov = (bool)std::fetestexcept(FE_OVERFLOW); - if (ppc_state.fpscr & 0x3) ppc_state.cr |= 0x2; if (set_result > 0.0) { - ppc_state.fpscr |= FPSCR::FPCC_POS; - } - else if (set_result < 0.0) { - ppc_state.fpscr |= FPSCR::FPCC_NEG; - } - else { - ppc_state.fpscr |= FPSCR::FPCC_ZERO; - } + ppc_state.fpscr |= FPCC_POS; + } else if (set_result < 0.0) { + ppc_state.fpscr |= FPCC_NEG; + } else { + ppc_state.fpscr |= FPCC_ZERO; + } if (isnan(set_result) || isinf(set_result)) { - ppc_state.fpscr |= FPSCR::FPCC_FPRCD; - } - - if (confirm_ov) { - // ppc_state.fpscr |= (FPSCR::FX | (FPSCR::FPRF & FPSCR::FPCC_FUNAN)); - } - - if (confirm_arc) { - //ppc_state.fpscr |= (FPSCR::FX | FPSCR::FPRF); - //ppc_state.fpscr &= 0xFFFF0FFF; + ppc_state.fpscr |= FPCC_FPRCD; } } -void ppc_changecrf1() { - ppc_state.cr &= ~((uint32_t)CR_select::CR1_field); - ppc_state.cr |= (ppc_state.fpscr & (uint32_t)CR_select::CR0_field) >> 4; +void ppc_changecrf1(double set_result) { + cmp_c = 0; + + /* + if (isnan(set_result)) { + cmp_c |= (1 << CRx_bit::CR_SO); + } + + if (set_result > 0.0) { + cmp_c |= (1 << CRx_bit::CR_GT); + } + + if (set_result < 0.0) { + cmp_c |= (1 << CRx_bit::CR_LT); + } + + if (set_result == 0.0) { + cmp_c |= (1 << CRx_bit::CR_EQ); + }*/ + + ppc_state.cr = ((ppc_state.cr & ~(CR_select::CR1_field)) | ((cmp_c) >> crf_d)); } // Floating Point Arithmetic void dppc_interpreter::ppc_fadd() { ppc_grab_regsfpdab(); - ppc_dblresult64_d = val_reg_a + val_reg_b; + ppc_dblresult64_d = double(val_reg_a + val_reg_b); - if (!isnan(ppc_dblresult64_d)) { + if (!isnan(ppc_dblresult64_d) || !isinf(ppc_dblresult64_d)) { ppc_store_dfpresult_flt(reg_d); - fpresult_update(ppc_dblresult64_d, rc_flag); - } else { + fpresult_update(ppc_dblresult64_d, rc_flag); + } + else { ppc_confirm_inf_nan(reg_a, reg_b, 0, rc_flag); } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fsub() { ppc_grab_regsfpdab(); - ppc_dblresult64_d = val_reg_a - val_reg_b; + ppc_dblresult64_d = double(val_reg_a - val_reg_b); - if (!isnan(ppc_dblresult64_d)) { + if (!isnan(ppc_dblresult64_d) || !isinf(ppc_dblresult64_d)) { ppc_store_dfpresult_flt(reg_d); - fpresult_update(ppc_dblresult64_d, rc_flag); + fpresult_update(ppc_dblresult64_d, rc_flag); } else { ppc_confirm_inf_nan(reg_a, reg_b, 0, rc_flag); } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fdiv() { @@ -311,13 +318,13 @@ void dppc_interpreter::ppc_fdiv() { if (!isnan(ppc_dblresult64_d) || !isinf(ppc_dblresult64_d)) { ppc_store_dfpresult_flt(reg_d); - fpresult_update(ppc_dblresult64_d, rc_flag); + fpresult_update(ppc_dblresult64_d, rc_flag); } else { ppc_confirm_inf_nan(reg_a, reg_b, 0, rc_flag); } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fmul() { @@ -325,15 +332,15 @@ void dppc_interpreter::ppc_fmul() { ppc_dblresult64_d = val_reg_a * val_reg_c; - if (!isnan(ppc_dblresult64_d)) { + if (!isnan(ppc_dblresult64_d) || !isinf(ppc_dblresult64_d)) { ppc_store_dfpresult_flt(reg_d); - fpresult_update(ppc_dblresult64_d, rc_flag); + fpresult_update(ppc_dblresult64_d, rc_flag); } else { ppc_confirm_inf_nan(reg_a, reg_b, 0, rc_flag); } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fmadd() { @@ -341,15 +348,15 @@ void dppc_interpreter::ppc_fmadd() { ppc_dblresult64_d = std::fma(val_reg_a, val_reg_c, val_reg_b); - if (!isnan(ppc_dblresult64_d)) { + if (!isnan(ppc_dblresult64_d) || !isinf(ppc_dblresult64_d)) { ppc_store_dfpresult_flt(reg_d); - fpresult_update(ppc_dblresult64_d, rc_flag); + fpresult_update(ppc_dblresult64_d, rc_flag); } else { ppc_confirm_inf_nan(reg_a, reg_b, reg_c); } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fmsub() { @@ -358,15 +365,15 @@ void dppc_interpreter::ppc_fmsub() { ppc_dblresult64_d = (val_reg_a * val_reg_c); ppc_dblresult64_d -= val_reg_b; - if (!isnan(ppc_dblresult64_d)) { + if (!isnan(ppc_dblresult64_d) || !isinf(ppc_dblresult64_d)) { ppc_store_dfpresult_flt(reg_d); - fpresult_update(ppc_dblresult64_d, rc_flag); + fpresult_update(ppc_dblresult64_d, rc_flag); } else { ppc_confirm_inf_nan(reg_a, reg_b, reg_c); } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fnmadd() { @@ -376,16 +383,16 @@ void dppc_interpreter::ppc_fnmadd() { ppc_dblresult64_d += val_reg_b; ppc_dblresult64_d = -(ppc_dblresult64_d); - if (!isnan(ppc_dblresult64_d)) { + if (!isnan(ppc_dblresult64_d) || !isinf(ppc_dblresult64_d)) { ppc_store_dfpresult_flt(reg_d); - fpresult_update(ppc_dblresult64_d, rc_flag); + fpresult_update(ppc_dblresult64_d, rc_flag); } else { ppc_confirm_inf_nan(reg_a, reg_b, reg_c); } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fnmsub() { @@ -395,31 +402,32 @@ void dppc_interpreter::ppc_fnmsub() { ppc_dblresult64_d -= val_reg_b; ppc_dblresult64_d = -(ppc_dblresult64_d); - if (!isnan(ppc_dblresult64_d)) { + if (!isnan(ppc_dblresult64_d) || !isinf(ppc_dblresult64_d)) { ppc_store_dfpresult_flt(reg_d); - fpresult_update(ppc_dblresult64_d, rc_flag); + fpresult_update(ppc_dblresult64_d, rc_flag); } else { ppc_confirm_inf_nan(reg_a, reg_b, reg_c); } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fadds() { ppc_grab_regsfpdab(); - ppc_dblresult64_d = (float)(val_reg_a + val_reg_b); + ppc_dblresult64_d = (float)(val_reg_a + val_reg_b); if (!isnan(ppc_dblresult64_d)) { ppc_store_sfpresult_flt(reg_d); - fpresult_update(ppc_dblresult64_d, rc_flag); - } else { + fpresult_update(ppc_dblresult64_d, rc_flag); + } + else { ppc_confirm_inf_nan(reg_a, reg_b, 0); } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fsubs() { @@ -429,13 +437,13 @@ void dppc_interpreter::ppc_fsubs() { if (!isnan(ppc_dblresult64_d)) { ppc_store_sfpresult_flt(reg_d); - fpresult_update(ppc_dblresult64_d, rc_flag); + fpresult_update(ppc_dblresult64_d, rc_flag); } else { ppc_confirm_inf_nan(reg_a, reg_b, 0); } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fdivs() { @@ -445,13 +453,13 @@ void dppc_interpreter::ppc_fdivs() { if (!isnan(ppc_dblresult64_d)) { ppc_store_sfpresult_flt(reg_d); - fpresult_update(ppc_dblresult64_d, rc_flag); + fpresult_update(ppc_dblresult64_d, rc_flag); } else { ppc_confirm_inf_nan(reg_a, reg_b, 0); } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fmuls() { @@ -461,13 +469,13 @@ void dppc_interpreter::ppc_fmuls() { if (!isnan(ppc_dblresult64_d)) { ppc_store_sfpresult_flt(reg_d); - fpresult_update(ppc_dblresult64_d, rc_flag); + fpresult_update(ppc_dblresult64_d, rc_flag); } else { ppc_confirm_inf_nan(reg_a, 0, reg_c); } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fmadds() { @@ -478,31 +486,31 @@ void dppc_interpreter::ppc_fmadds() { if (!isnan(ppc_dblresult64_d)) { ppc_store_sfpresult_flt(reg_d); - fpresult_update(ppc_dblresult64_d, rc_flag); + fpresult_update(ppc_dblresult64_d, rc_flag); } else { ppc_confirm_inf_nan(reg_a, reg_b, reg_c); } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fmsubs() { ppc_grab_regsfpdabc(); - float intermediate = (float)val_reg_a * (float)val_reg_c; + float intermediate = float(val_reg_a * val_reg_c); intermediate -= (float)val_reg_b; ppc_dblresult64_d = static_cast(intermediate); if (!isnan(ppc_dblresult64_d)) { ppc_store_sfpresult_flt(reg_d); - fpresult_update(ppc_dblresult64_d, rc_flag); + fpresult_update(ppc_dblresult64_d, rc_flag); } else { ppc_confirm_inf_nan(reg_a, reg_b, reg_c); } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fnmadds() { @@ -515,13 +523,13 @@ void dppc_interpreter::ppc_fnmadds() { if (!isnan(ppc_dblresult64_d)) { ppc_store_sfpresult_flt(reg_d); - fpresult_update(ppc_dblresult64_d, rc_flag); + fpresult_update(ppc_dblresult64_d, rc_flag); } else { ppc_confirm_inf_nan(reg_a, reg_b, reg_c); } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fnmsubs() { @@ -535,13 +543,13 @@ void dppc_interpreter::ppc_fnmsubs() { if (!isnan(ppc_dblresult64_d)) { ppc_store_sfpresult_flt(reg_d); - fpresult_update(ppc_dblresult64_d, rc_flag); + fpresult_update(ppc_dblresult64_d, rc_flag); } else { ppc_confirm_inf_nan(reg_a, reg_b, reg_c); } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fabs() { @@ -552,7 +560,7 @@ void dppc_interpreter::ppc_fabs() { ppc_store_dfpresult_flt(reg_d); if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fnabs() { @@ -564,7 +572,7 @@ void dppc_interpreter::ppc_fnabs() { ppc_store_dfpresult_flt(reg_d); if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fneg() { @@ -575,7 +583,7 @@ void dppc_interpreter::ppc_fneg() { ppc_store_dfpresult_flt(reg_d); if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fsel() { @@ -586,7 +594,7 @@ void dppc_interpreter::ppc_fsel() { ppc_store_dfpresult_flt(reg_d); if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fsqrt() { @@ -595,7 +603,7 @@ void dppc_interpreter::ppc_fsqrt() { ppc_store_dfpresult_flt(reg_d); if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fsqrts() { @@ -608,7 +616,7 @@ void dppc_interpreter::ppc_fsqrts() { ppc_store_sfpresult_flt(reg_d); if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_frsqrte() { @@ -622,7 +630,7 @@ void dppc_interpreter::ppc_frsqrte() { ppc_store_dfpresult_flt(reg_d); if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_frsp() { @@ -631,7 +639,7 @@ void dppc_interpreter::ppc_frsp() { ppc_store_dfpresult_flt(reg_d); if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fres() { @@ -654,7 +662,7 @@ void dppc_interpreter::ppc_fres() { } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fctiw() { @@ -694,7 +702,7 @@ void dppc_interpreter::ppc_fctiw() { } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } void dppc_interpreter::ppc_fctiwz() { @@ -720,7 +728,7 @@ void dppc_interpreter::ppc_fctiwz() { } if (rc_flag) - ppc_changecrf1(); + ppc_changecrf1(ppc_dblresult64_d); } // Floating Point Store and Load @@ -982,26 +990,30 @@ void dppc_interpreter::ppc_fcmpo() { ppc_grab_regsfpsab(); ppc_state.fpscr &= 0xFFFF0FFF; + cmp_c = 0; + crf_d = 4; if (std::isnan(db_test_a) || std::isnan(db_test_b)) { - cmp_c |= (1 << (uint32_t)CRx_bit::CR_SO); - } else if (db_test_a < db_test_b) { - cmp_c |= (1 << (uint32_t)CRx_bit::CR_LT); - } else if (db_test_a > db_test_b) { - cmp_c |= (1 << (uint32_t)CRx_bit::CR_GT); - } else { - cmp_c |= (1 << (uint32_t)CRx_bit::CR_EQ); + cmp_c |= (1 << CRx_bit::CR_SO); + } + + if (db_test_a < db_test_b) { + cmp_c |= (1 << CRx_bit::CR_LT); + } + else if (db_test_a > db_test_b) { + cmp_c |= (1 << CRx_bit::CR_GT); + } + else { + cmp_c |= (1 << CRx_bit::CR_EQ); } - fpresult_update(db_test_a, true); - - ppc_state.fpscr = (ppc_state.fpscr & ~(FPSCR::FPRF)) | (cmp_c << 12); - ppc_state.cr = - ((ppc_state.cr & ~((uint32_t)CR_select::CR0_field >> crf_d)) | ((cmp_c + xercon) >> crf_d)); + ppc_state.fpscr &= ~(FPSCR::FPRF); + ppc_state.fpscr |= (cmp_c << 12); + ppc_state.cr = ((ppc_state.cr & ~(0xF0000000 >> crf_d)) | ((cmp_c) >> crf_d)); if (std::isnan(db_test_a) || std::isnan(db_test_b)) { - ppc_state.fpscr |= FPSCR::VXSNAN; - if (ppc_state.fpscr & 0x80) { + ppc_state.fpscr |= FPSCR::FX | FPSCR::VXSNAN; + if ((ppc_state.fpscr & FPSCR::VE) == 0) { ppc_state.fpscr |= FPSCR::VXVC; } } else if ((db_test_a == qnan) || (db_test_b == qnan)) { @@ -1012,25 +1024,28 @@ void dppc_interpreter::ppc_fcmpo() { void dppc_interpreter::ppc_fcmpu() { ppc_grab_regsfpsab(); - ppc_state.fpscr &= 0xFFFF0FFF; + cmp_c = 0; + crf_d = 4; if (std::isnan(db_test_a) || std::isnan(db_test_b)) { - cmp_c |= (1 << (uint32_t)CRx_bit::CR_SO); - } else if (db_test_a < db_test_b) { - cmp_c |= (1 << (uint32_t)CRx_bit::CR_LT); - } else if (db_test_a > db_test_b) { - cmp_c |= (1 << (uint32_t)CRx_bit::CR_GT); - } else { - cmp_c |= (1 << (uint32_t)CRx_bit::CR_EQ); + cmp_c |= (1 << CRx_bit::CR_SO); + } + + if (db_test_a < db_test_b) { + cmp_c |= (1 << CRx_bit::CR_LT); + } + else if (db_test_a > db_test_b) { + cmp_c |= (1 << CRx_bit::CR_GT); + } + else { + cmp_c |= (1 << CRx_bit::CR_EQ); } - fpresult_update(db_test_a, true); + ppc_state.fpscr &= ~(FPSCR::FPRF); + ppc_state.fpscr |= (cmp_c << 12); + ppc_state.cr = ((ppc_state.cr & ~(0xF0000000 >> crf_d)) | ((cmp_c) >> crf_d)); - ppc_state.fpscr = (ppc_state.fpscr & ~(FPSCR::FPRF)) | (cmp_c << 12); - ppc_state.cr = - ((ppc_state.cr & ~((uint32_t)CR_select::CR0_field >> crf_d)) | ((cmp_c + xercon) >> crf_d)); - - if (std::isnan(db_test_a) || std::isnan(db_test_b)) { - ppc_state.fpscr |= FPSCR::VXSNAN; - } + //if (std::isnan(db_test_a) || std::isnan(db_test_b)) { + // ppc_state.fpscr |= FPSCR::VX | FPSCR::VXSNAN; + //} } diff --git a/cpu/ppc/test/genppctests.py b/cpu/ppc/test/genppctests.py index e1a30f3..ab01825 100644 --- a/cpu/ppc/test/genppctests.py +++ b/cpu/ppc/test/genppctests.py @@ -112,9 +112,9 @@ def gen_ppc_opcode(opc_str, imm): elif opc_str == "FADDS.": return (0x3B << 26) + (3 << 21) + (3 << 16) + (4 << 11) + (0x15 << 1) + 1 elif opc_str == "FCMPO": - return (0x3F << 26) + (3 << 16) + (4 << 11) + (0x20 << 1) + return (0x3F << 26)+ (4 << 21) + (3 << 16) + (4 << 11) + (0x20 << 1) elif opc_str == "FCMPU": - return (0x3F << 26) + (3 << 16) + (4 << 11) + return (0x3F << 26)+ (4 << 21) + (3 << 16) + (4 << 11) elif opc_str == "FCTIW": return (0x3B << 26) + (3 << 16) + (4 << 11) + (0xE << 1) elif opc_str == "FCTIW.": @@ -181,14 +181,16 @@ def gen_ppc_opcode(opc_str, imm): return (0x3F << 26) + (3 << 21) + (3 << 16) + (4 << 11) + (5 << 6) + (0x1C << 1) elif opc_str == "FNMSUBS.": return (0x3F << 26) + (3 << 21) + (3 << 16) + (4 << 11) + (5 << 6) + (0x1C << 1) + 1 + elif opc_str == "FRES": + return (0x3B << 26) + (3 << 21) + (4 << 11) + (0x15 << 1) elif opc_str == "FSUB": - return (0x3F << 26) + (3 << 21) + (3 << 16) + (4 << 11) + (0x15 << 1) + return (0x3F << 26) + (3 << 21) + (3 << 16) + (4 << 11) + (0x14 << 1) elif opc_str == "FSUB.": - return (0x3F << 26) + (3 << 21) + (3 << 16) + (4 << 11) + (0x15 << 1) + 1 + return (0x3F << 26) + (3 << 21) + (3 << 16) + (4 << 11) + (0x14 << 1) + 1 elif opc_str == "FSUBS": - return (0x3B << 26) + (3 << 21) + (3 << 16) + (4 << 11) + (0x15 << 1) + return (0x3B << 26) + (3 << 21) + (3 << 16) + (4 << 11) + (0x14 << 1) elif opc_str == "FSUBS.": - return (0x3B << 26) + (3 << 21) + (3 << 16) + (4 << 11) + (0x15 << 1) + 1 + return (0x3B << 26) + (3 << 21) + (3 << 16) + (4 << 11) + (0x14 << 1) + 1 elif opc_str == "MULHW": return (0x1F << 26) + (3 << 21) + (3 << 16) + (4 << 11) + (0x4B << 1) elif opc_str == "MULHW.": diff --git a/cpu/ppc/test/ppcfloattests.csv b/cpu/ppc/test/ppcfloattests.csv index 033ad2c..9afdbee 100644 --- a/cpu/ppc/test/ppcfloattests.csv +++ b/cpu/ppc/test/ppcfloattests.csv @@ -1688,367 +1688,367 @@ FNMSUBS.,0xFC632179,round=RTZ,frD=0xFFF0000000000000,frA=1.000000e+00,frC=1.0000 FNMSUBS.,0xFC632179,round=RPI,frD=0xFFF0000000000000,frA=1.000000e+00,frC=1.000000e+00,frB=-inf,FPSCR=0x00009002,CR=0x00000002 FNMSUBS.,0xFC632179,round=RNI,frD=0xFFF0000000000000,frA=1.000000e+00,frC=1.000000e+00,frB=-inf,FPSCR=0x00009003,CR=0x00000002 FNMSUBS.,0xFC632179,round=VEN,frD=0xFFF0000000000000,frA=1.000000e+00,frC=1.000000e+00,frB=-inf,FPSCR=0x00009080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0x0000000000000000,frA=0.000000e+00,frB=0.000000e+00,FPSCR=0x00002000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0x0000000000000000,frA=0.000000e+00,frB=0.000000e+00,FPSCR=0x00002001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0x0000000000000000,frA=0.000000e+00,frB=0.000000e+00,FPSCR=0x00002002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0x8000000000000000,frA=0.000000e+00,frB=0.000000e+00,FPSCR=0x00012003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0x0000000000000000,frA=0.000000e+00,frB=0.000000e+00,FPSCR=0x00002080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0x0000000000000000,frA=5.000000e-01,frB=5.000000e-01,FPSCR=0x00002000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0x0000000000000000,frA=5.000000e-01,frB=5.000000e-01,FPSCR=0x00002001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0x0000000000000000,frA=5.000000e-01,frB=5.000000e-01,FPSCR=0x00002002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0x8000000000000000,frA=5.000000e-01,frB=5.000000e-01,FPSCR=0x00012003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0x0000000000000000,frA=5.000000e-01,frB=5.000000e-01,FPSCR=0x00002080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0x0000000000000000,frA=1.000000e+00,frB=1.000000e+00,FPSCR=0x00002000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0x0000000000000000,frA=1.000000e+00,frB=1.000000e+00,FPSCR=0x00002001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0x0000000000000000,frA=1.000000e+00,frB=1.000000e+00,FPSCR=0x00002002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0x8000000000000000,frA=1.000000e+00,frB=1.000000e+00,FPSCR=0x00012003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0x0000000000000000,frA=1.000000e+00,frB=1.000000e+00,FPSCR=0x00002080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0x0000000000000000,frA=3.500000e+00,frB=3.500000e+00,FPSCR=0x00002000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0x0000000000000000,frA=3.500000e+00,frB=3.500000e+00,FPSCR=0x00002001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0x0000000000000000,frA=3.500000e+00,frB=3.500000e+00,FPSCR=0x00002002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0x8000000000000000,frA=3.500000e+00,frB=3.500000e+00,FPSCR=0x00012003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0x0000000000000000,frA=3.500000e+00,frB=3.500000e+00,FPSCR=0x00002080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0x0000000000000000,frA=3.923640e-44,frB=3.923640e-44,FPSCR=0x00002000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0x0000000000000000,frA=3.923640e-44,frB=3.923640e-44,FPSCR=0x00002001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0x0000000000000000,frA=3.923640e-44,frB=3.923640e-44,FPSCR=0x00002002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0x8000000000000000,frA=3.923640e-44,frB=3.923640e-44,FPSCR=0x00012003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0x0000000000000000,frA=3.923640e-44,frB=3.923640e-44,FPSCR=0x00002080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0x0000000000000000,frA=1.797693e+308,frB=1.797693e+308,FPSCR=0x00002000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0x0000000000000000,frA=1.797693e+308,frB=1.797693e+308,FPSCR=0x00002001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0x0000000000000000,frA=1.797693e+308,frB=1.797693e+308,FPSCR=0x00002002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0x8000000000000000,frA=1.797693e+308,frB=1.797693e+308,FPSCR=0x00012003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0x0000000000000000,frA=1.797693e+308,frB=1.797693e+308,FPSCR=0x00002080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0x0000000000000000,frA=-1.797693e+308,frB=-1.797693e+308,FPSCR=0x00002000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0x0000000000000000,frA=-1.797693e+308,frB=-1.797693e+308,FPSCR=0x00002001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0x0000000000000000,frA=-1.797693e+308,frB=-1.797693e+308,FPSCR=0x00002002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0x8000000000000000,frA=-1.797693e+308,frB=-1.797693e+308,FPSCR=0x00012003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0x0000000000000000,frA=-1.797693e+308,frB=-1.797693e+308,FPSCR=0x00002080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0x7FF0000000000000,frA=1.797693e+308,frB=-1.797693e+308,FPSCR=0x92025000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0x7FEFFFFFFFFFFFFF,frA=1.797693e+308,frB=-1.797693e+308,FPSCR=0x92024001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0x7FF0000000000000,frA=1.797693e+308,frB=-1.797693e+308,FPSCR=0x92025002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0x7FEFFFFFFFFFFFFF,frA=1.797693e+308,frB=-1.797693e+308,FPSCR=0x92024003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0x7FF0000000000000,frA=1.797693e+308,frB=-1.797693e+308,FPSCR=0x92025080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0x7FFC000000000000,frA=nan,frB=inf,FPSCR=0xA1011000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0x7FFC000000000000,frA=nan,frB=inf,FPSCR=0xA1011001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0x7FFC000000000000,frA=nan,frB=inf,FPSCR=0xA1011002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0x7FFC000000000000,frA=nan,frB=inf,FPSCR=0xA1011003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0x0000000000000000,frA=nan,frB=inf,FPSCR=0xE1000080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0x7FF8000000000000,frA=nan,frB=inf,FPSCR=0x00011000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0x7FF8000000000000,frA=nan,frB=inf,FPSCR=0x00011001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0x7FF8000000000000,frA=nan,frB=inf,FPSCR=0x00011002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0x7FF8000000000000,frA=nan,frB=inf,FPSCR=0x00011003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0x7FF8000000000000,frA=nan,frB=inf,FPSCR=0x00011080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0x7FF8000000000000,frA=nan,frB=-inf,FPSCR=0x00011000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0x7FF8000000000000,frA=nan,frB=-inf,FPSCR=0x00011001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0x7FF8000000000000,frA=nan,frB=-inf,FPSCR=0x00011002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0x7FF8000000000000,frA=nan,frB=-inf,FPSCR=0x00011003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0x7FF8000000000000,frA=nan,frB=-inf,FPSCR=0x00011080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0x7FF8000000000000,frA=inf,frB=nan,FPSCR=0x00011000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0x7FF8000000000000,frA=inf,frB=nan,FPSCR=0x00011001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0x7FF8000000000000,frA=inf,frB=nan,FPSCR=0x00011002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0x7FF8000000000000,frA=inf,frB=nan,FPSCR=0x00011003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0x7FF8000000000000,frA=inf,frB=nan,FPSCR=0x00011080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0x7FF8000000000000,frA=-inf,frB=nan,FPSCR=0x00011000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0x7FF8000000000000,frA=-inf,frB=nan,FPSCR=0x00011001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0x7FF8000000000000,frA=-inf,frB=nan,FPSCR=0x00011002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0x7FF8000000000000,frA=-inf,frB=nan,FPSCR=0x00011003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0x7FF8000000000000,frA=-inf,frB=nan,FPSCR=0x00011080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0x7FF8000000000000,frA=inf,frB=inf,FPSCR=0xA0811000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0x7FF8000000000000,frA=inf,frB=inf,FPSCR=0xA0811001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0x7FF8000000000000,frA=inf,frB=inf,FPSCR=0xA0811002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0x7FF8000000000000,frA=inf,frB=inf,FPSCR=0xA0811003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0x0000000000000000,frA=inf,frB=inf,FPSCR=0xE0800080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0x7FF0000000000000,frA=inf,frB=-inf,FPSCR=0x00005000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0x7FF0000000000000,frA=inf,frB=-inf,FPSCR=0x00005001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0x7FF0000000000000,frA=inf,frB=-inf,FPSCR=0x00005002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0x7FF0000000000000,frA=inf,frB=-inf,FPSCR=0x00005003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0x7FF0000000000000,frA=inf,frB=-inf,FPSCR=0x00005080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0xFFF0000000000000,frA=-inf,frB=inf,FPSCR=0x00009000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0xFFF0000000000000,frA=-inf,frB=inf,FPSCR=0x00009001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0xFFF0000000000000,frA=-inf,frB=inf,FPSCR=0x00009002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0xFFF0000000000000,frA=-inf,frB=inf,FPSCR=0x00009003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0xFFF0000000000000,frA=-inf,frB=inf,FPSCR=0x00009080,CR=0x00000000 -FSUB,0xFC63202A,round=RTN,frD=0x7FF8000000000000,frA=-inf,frB=-inf,FPSCR=0xA0811000,CR=0x00000000 -FSUB,0xFC63202A,round=RTZ,frD=0x7FF8000000000000,frA=-inf,frB=-inf,FPSCR=0xA0811001,CR=0x00000002 -FSUB,0xFC63202A,round=RPI,frD=0x7FF8000000000000,frA=-inf,frB=-inf,FPSCR=0xA0811002,CR=0x00000002 -FSUB,0xFC63202A,round=RNI,frD=0x7FF8000000000000,frA=-inf,frB=-inf,FPSCR=0xA0811003,CR=0x00000002 -FSUB,0xFC63202A,round=VEN,frD=0x0000000000000000,frA=-inf,frB=-inf,FPSCR=0xE0800080,CR=0x00000000 -FSUB.,0xFC63202B,round=RTN,frD=0x0000000000000000,frA=0.000000e+00,frB=0.000000e+00,FPSCR=0x00002000,CR=0x00000000 -FSUB.,0xFC63202B,round=RTZ,frD=0x0000000000000000,frA=0.000000e+00,frB=0.000000e+00,FPSCR=0x00002001,CR=0x00000002 -FSUB.,0xFC63202B,round=RPI,frD=0x0000000000000000,frA=0.000000e+00,frB=0.000000e+00,FPSCR=0x00002002,CR=0x00000002 -FSUB.,0xFC63202B,round=RNI,frD=0x8000000000000000,frA=0.000000e+00,frB=0.000000e+00,FPSCR=0x00012003,CR=0x00000002 -FSUB.,0xFC63202B,round=VEN,frD=0x0000000000000000,frA=0.000000e+00,frB=0.000000e+00,FPSCR=0x00002080,CR=0x00000000 -FSUB.,0xFC63202B,round=RTN,frD=0x0000000000000000,frA=5.000000e-01,frB=5.000000e-01,FPSCR=0x00002000,CR=0x00000000 -FSUB.,0xFC63202B,round=RTZ,frD=0x0000000000000000,frA=5.000000e-01,frB=5.000000e-01,FPSCR=0x00002001,CR=0x00000002 -FSUB.,0xFC63202B,round=RPI,frD=0x0000000000000000,frA=5.000000e-01,frB=5.000000e-01,FPSCR=0x00002002,CR=0x00000002 -FSUB.,0xFC63202B,round=RNI,frD=0x8000000000000000,frA=5.000000e-01,frB=5.000000e-01,FPSCR=0x00012003,CR=0x00000002 -FSUB.,0xFC63202B,round=VEN,frD=0x0000000000000000,frA=5.000000e-01,frB=5.000000e-01,FPSCR=0x00002080,CR=0x00000000 -FSUB.,0xFC63202B,round=RTN,frD=0x0000000000000000,frA=1.000000e+00,frB=1.000000e+00,FPSCR=0x00002000,CR=0x00000000 -FSUB.,0xFC63202B,round=RTZ,frD=0x0000000000000000,frA=1.000000e+00,frB=1.000000e+00,FPSCR=0x00002001,CR=0x00000002 -FSUB.,0xFC63202B,round=RPI,frD=0x0000000000000000,frA=1.000000e+00,frB=1.000000e+00,FPSCR=0x00002002,CR=0x00000002 -FSUB.,0xFC63202B,round=RNI,frD=0x8000000000000000,frA=1.000000e+00,frB=1.000000e+00,FPSCR=0x00012003,CR=0x00000002 -FSUB.,0xFC63202B,round=VEN,frD=0x0000000000000000,frA=1.000000e+00,frB=1.000000e+00,FPSCR=0x00002080,CR=0x00000000 -FSUB.,0xFC63202B,round=RTN,frD=0x0000000000000000,frA=3.500000e+00,frB=3.500000e+00,FPSCR=0x00002000,CR=0x00000000 -FSUB.,0xFC63202B,round=RTZ,frD=0x0000000000000000,frA=3.500000e+00,frB=3.500000e+00,FPSCR=0x00002001,CR=0x00000002 -FSUB.,0xFC63202B,round=RPI,frD=0x0000000000000000,frA=3.500000e+00,frB=3.500000e+00,FPSCR=0x00002002,CR=0x00000002 -FSUB.,0xFC63202B,round=RNI,frD=0x8000000000000000,frA=3.500000e+00,frB=3.500000e+00,FPSCR=0x00012003,CR=0x00000002 -FSUB.,0xFC63202B,round=VEN,frD=0x0000000000000000,frA=3.500000e+00,frB=3.500000e+00,FPSCR=0x00002080,CR=0x00000000 -FSUB.,0xFC63202B,round=RTN,frD=0x0000000000000000,frA=3.923640e-44,frB=3.923640e-44,FPSCR=0x00002000,CR=0x00000000 -FSUB.,0xFC63202B,round=RTZ,frD=0x0000000000000000,frA=3.923640e-44,frB=3.923640e-44,FPSCR=0x00002001,CR=0x00000002 -FSUB.,0xFC63202B,round=RPI,frD=0x0000000000000000,frA=3.923640e-44,frB=3.923640e-44,FPSCR=0x00002002,CR=0x00000002 -FSUB.,0xFC63202B,round=RNI,frD=0x8000000000000000,frA=3.923640e-44,frB=3.923640e-44,FPSCR=0x00012003,CR=0x00000002 -FSUB.,0xFC63202B,round=VEN,frD=0x0000000000000000,frA=3.923640e-44,frB=3.923640e-44,FPSCR=0x00002080,CR=0x00000000 -FSUB.,0xFC63202B,round=RTN,frD=0x0000000000000000,frA=1.797693e+308,frB=1.797693e+308,FPSCR=0x00002000,CR=0x00000000 -FSUB.,0xFC63202B,round=RTZ,frD=0x0000000000000000,frA=1.797693e+308,frB=1.797693e+308,FPSCR=0x00002001,CR=0x00000002 -FSUB.,0xFC63202B,round=RPI,frD=0x0000000000000000,frA=1.797693e+308,frB=1.797693e+308,FPSCR=0x00002002,CR=0x00000002 -FSUB.,0xFC63202B,round=RNI,frD=0x8000000000000000,frA=1.797693e+308,frB=1.797693e+308,FPSCR=0x00012003,CR=0x00000002 -FSUB.,0xFC63202B,round=VEN,frD=0x0000000000000000,frA=1.797693e+308,frB=1.797693e+308,FPSCR=0x00002080,CR=0x00000000 -FSUB.,0xFC63202B,round=RTN,frD=0x0000000000000000,frA=-1.797693e+308,frB=-1.797693e+308,FPSCR=0x00002000,CR=0x00000000 -FSUB.,0xFC63202B,round=RTZ,frD=0x0000000000000000,frA=-1.797693e+308,frB=-1.797693e+308,FPSCR=0x00002001,CR=0x00000002 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+FCMPU,0xFC832000,frA=nan,frB=nan,FPSCR=0x00001000,CR=0x01000000 +FCMPU,0xFC832000,frA=nan,frB=nan,FPSCR=0xA1001000,CR=0x01000000 +FCMPU,0xFC832000,frA=inf,frB=inf,FPSCR=0x00002000,CR=0x02000000 +FCMPU,0xFC832000,frA=inf,frB=-inf,FPSCR=0x00004000,CR=0x04000000 +FCMPU,0xFC832000,frA=-inf,frB=inf,FPSCR=0x00008000,CR=0x08000000 +FCMPU,0xFC832000,frA=-inf,frB=-inf,FPSCR=0x00002000,CR=0x02000000 diff --git a/cpu/ppc/test/ppctests.cpp b/cpu/ppc/test/ppctests.cpp index 8430979..579cbf8 100644 --- a/cpu/ppc/test/ppctests.cpp +++ b/cpu/ppc/test/ppctests.cpp @@ -229,7 +229,7 @@ static void read_test_float_data() { dfp_src3 = stod(tokens[i].substr(4), NULL); } else if (tokens[i].rfind("round=", 0) == 0) { rounding_mode = tokens[i].substr(6, 3); - ppc_state.fpscr &= 0xFFFFFFFC; + ppc_state.fpscr = 0; if (rounding_mode.compare("RTN") == 0) { ppc_state.fpscr = 0x0; } else if (rounding_mode.compare("RTZ") == 0) { @@ -263,7 +263,7 @@ static void read_test_float_data() { ppc_state.fpr[4].dbl64_r = dfp_src2; ppc_state.fpr[5].dbl64_r = dfp_src3; - ppc_state.cr = 0; + ppc_state.cr = 0; ppc_cur_instruction = opcode; @@ -303,6 +303,9 @@ int main() { read_test_data(); + cout << endl << "Float IEEE suport: " << (bool)std::numeric_limits::is_iec559 << endl; + cout << endl << "Double IEEE suport: " << (bool)std::numeric_limits::is_iec559 << endl; + cout << endl << "Testing floating point instructions:" << endl; read_test_float_data();