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Fixed shifting ops and eieio

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This commit is contained in:
dingusdev 2020-02-12 20:26:12 -07:00
parent e4ee252b6c
commit c2eafcc45d
2 changed files with 13 additions and 3 deletions
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9
cpu/ppc/ppcdisasm.cpp
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@ -858,13 +858,16 @@ void opc_group31(PPCDisasmContext* ctx)
if (rc_set)
strcat(opcode, ".");
switch (index) {
case 0: case 4: case 6: case 16:
case 20: case 22: case 24: case 28:
fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
break;
case 5: case 7: case 21: case 23:
case 25: case 29:
fmt_threeop_uimm(ctx->instr_str, opcode, rs, ra, rb);
fmt_threeop_simm(ctx->instr_str, opcode, ra, rs, rb);
break;
default:
opc_illegal(ctx);
}
@ -940,7 +943,7 @@ void opc_group31(PPCDisasmContext* ctx)
return;
break;
}
else if (index == 18) {
else if ((index == 18) | (index == 26)) {
ctx->instr_str = my_sprintf("%-8s", opcode);
return;
}

7
cpu/ppc/test/ppcdisasmtest.csv
View File

@ -6,6 +6,7 @@
# unconditional branches
0xFFF03008,0x48000355,bl,0xFFF0335C
0xFFF03000,0x4280035C,b,0xFFF0335C
0xFFF03000,0x48000802,ba,0x00000800
# bcctr variants with simplified mnemonics
0xFFF03000,0x4E800420,bctr
@ -191,6 +192,11 @@
0xFFF00100,0x7D080120,mtcrf,0x80,r8
0xFFF00100,0x7E007120,mtcrf,0x07,r16
# shift instructions, primary opcode 0x1F
0xFFF00100,0x7C65FE70,srawi,r5,r3,0x1F
0xFFF00100,0x7D6B1E70,srawi,r11,r11,0x3
0xFFF00100,0x7C090E71,srawi.,r9,r0,0x1
# logical instructions, primary opcode 0x1F
0xFFF00100,0x7FC32838,and,r3,r30,r5
0xFFF00100,0x7C672039,and.,r7,r3,r4
@ -211,6 +217,7 @@
# synchronization instructions
0xFFF03000,0x4C00012C,isync
0xFFF00100,7C0006AC,eieio
# trap instructions
0xFFF00100,0x7F800008,tw,28,r0,r0

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