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https://github.com/dingusdev/dingusppc.git
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amic: reorganize registers in blocks.
This commit is contained in:
Maxim Poliakovski
parent
2f725fe3e4
commit
c7544d9c2f
146
devices/amic.cpp
146
devices/amic.cpp
@ -66,29 +66,41 @@ uint32_t AMIC::read(uint32_t reg_start, uint32_t offset, int size)
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{
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{
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uint32_t phase_val;
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uint32_t phase_val;
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if (offset < 0x2000) {
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// subdevices registers
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switch(offset >> 12) {
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case 0: // VIA1 registers
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case 1:
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return this->viacuda->read(offset >> 9);
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return this->viacuda->read(offset >> 9);
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case 4: // SCC registers
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LOG_F(WARNING, "AMIC: read attempt from unimplemented SCC register");
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return 0;
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case 0x10: // SCSI registers
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LOG_F(WARNING, "AMIC: read attempt from unimplemented SCSI register");
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return 0;
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case 0x14: // Sound registers
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switch (offset) {
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case AMICReg::Snd_Stat_0:
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case AMICReg::Snd_Stat_1:
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case AMICReg::Snd_Stat_2:
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return (this->awacs->read_stat() >> (offset & 3 * 8)) & 0xFF;
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case AMICReg::Snd_Phase0:
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case AMICReg::Snd_Phase1:
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case AMICReg::Snd_Phase2:
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// the sound phase register is organized as follows:
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// 000000oo oooooooo oopppppp where 'o' is the 12-bit offset
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// into the DMA buffer and 'p' is an undocumented prescale value
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// HWInit doesn't care about. Let's hope it will be sufficient
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// to return 0 for prescale.
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phase_val = this->snd_out_dma->get_cur_buf_pos() << 6;
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return (phase_val >> ((2 - (offset & 3)) * 8)) & 0xFF;
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case AMICReg::Snd_Out_Ctrl:
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return this->snd_out_ctrl;
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case AMICReg::Snd_Out_DMA:
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return this->snd_out_dma->read_stat();
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}
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}
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}
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switch(offset) {
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switch(offset) {
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case AMICReg::Snd_Stat_0:
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case AMICReg::Snd_Stat_1:
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case AMICReg::Snd_Stat_2:
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return (this->awacs->read_stat() >> (offset & 3 * 8)) & 0xFF;
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case AMICReg::Snd_Phase0:
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case AMICReg::Snd_Phase1:
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case AMICReg::Snd_Phase2:
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// the sound phase register is organized as follows:
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// 000000oo oooooooo oopppppp where 'o' is the 12-bit offset
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// into the DMA buffer and 'p' is an undocumented prescale value
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// HWInit doesn't care about. Let's hope it will be sufficient
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// to return 0 for prescale.
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phase_val = this->snd_out_dma->get_cur_buf_pos() << 6;
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return (phase_val >> ((2 - (offset & 3)) * 8)) & 0xFF;
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case AMICReg::Snd_Out_Ctrl:
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return this->snd_out_ctrl;
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case AMICReg::Snd_Out_DMA:
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return this->snd_out_dma->read_stat();
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case AMICReg::Diag_Reg:
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case AMICReg::Diag_Reg:
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return 0xFFU; // this value allows the machine to boot normally
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return 0xFFU; // this value allows the machine to boot normally
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case AMICReg::SCSI_DMA_Ctrl:
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case AMICReg::SCSI_DMA_Ctrl:
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@ -103,56 +115,62 @@ void AMIC::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size)
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{
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{
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uint32_t mask;
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uint32_t mask;
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if (offset < 0x2000) {
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// subdevices registers
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switch(offset >> 12) {
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case 0: // VIA1 registers
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case 1:
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this->viacuda->write(offset >> 9, value);
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this->viacuda->write(offset >> 9, value);
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return;
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return;
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case 0x14: // Sound registers
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switch(offset) {
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case AMICReg::Snd_Ctrl_0:
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case AMICReg::Snd_Ctrl_1:
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case AMICReg::Snd_Ctrl_2:
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// remember values of sound control registers
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this->imm_snd_regs[offset & 3] = value;
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// transfer control information to the sound codec when ready
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if ((this->imm_snd_regs[0] & 0xC0) == PDM_SND_CTRL_VALID) {
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this->awacs->write_ctrl(
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(this->imm_snd_regs[1] >> 4) | (this->imm_snd_regs[0] & 0x3F),
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((this->imm_snd_regs[1] & 0xF) << 8) | this->imm_snd_regs[2]
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);
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}
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return;
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case AMICReg::Snd_Buf_Size_Hi:
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case AMICReg::Snd_Buf_Size_Lo:
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mask = 0xFF00U >> (8 * (offset & 1));
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this->snd_buf_size = (this->snd_buf_size & ~mask) |
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((value & 0xFF) << (8 * ((offset & 1) ^1)));
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this->snd_buf_size &= ~3; // sound buffer size is always a multiple of 4
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LOG_F(9, "AMIC: Sound buffer size set to 0x%X", this->snd_buf_size);
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return;
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case AMICReg::Snd_Out_Ctrl:
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LOG_F(9, "AMIC Sound Out Ctrl updated, val=%x", value);
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if ((value & 1) != (this->snd_out_ctrl & 1)) {
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if (value & 1) {
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LOG_F(9, "AMIC Sound Out DMA enabled!");
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this->snd_out_dma->init(this->dma_base & ~0x3FFFF,
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this->snd_buf_size);
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this->snd_out_dma->enable();
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this->awacs->set_sample_rate((this->snd_out_ctrl >> 1) & 3);
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this->awacs->start_output_dma();
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} else {
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LOG_F(9, "AMIC Sound Out DMA disabled!");
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this->snd_out_dma->disable();
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}
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}
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this->snd_out_ctrl = value;
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return;
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case AMICReg::Snd_In_Ctrl:
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LOG_F(INFO, "AMIC Sound In Ctrl updated, val=%x", value);
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return;
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case AMICReg::Snd_Out_DMA:
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this->snd_out_dma->write_dma_out_ctrl(value);
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return;
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}
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}
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}
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switch(offset) {
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switch(offset) {
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case AMICReg::Snd_Ctrl_0:
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case AMICReg::Snd_Ctrl_1:
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case AMICReg::Snd_Ctrl_2:
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// remember values of sound control registers
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this->imm_snd_regs[offset & 3] = value;
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// transfer control information to the sound codec when ready
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if ((this->imm_snd_regs[0] & 0xC0) == PDM_SND_CTRL_VALID) {
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this->awacs->write_ctrl(
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(this->imm_snd_regs[1] >> 4) | (this->imm_snd_regs[0] & 0x3F),
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((this->imm_snd_regs[1] & 0xF) << 8) | this->imm_snd_regs[2]
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);
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}
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break;
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case AMICReg::Snd_Buf_Size_Hi:
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case AMICReg::Snd_Buf_Size_Lo:
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mask = 0xFF00U >> (8 * (offset & 1));
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this->snd_buf_size = (this->snd_buf_size & ~mask) |
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((value & 0xFF) << (8 * ((offset & 1) ^1)));
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this->snd_buf_size &= ~3; // sound buffer size is always a multiple of 4
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LOG_F(9, "AMIC: Sound buffer size set to 0x%X", this->snd_buf_size);
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break;
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case AMICReg::Snd_Out_Ctrl:
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LOG_F(9, "AMIC Sound Out Ctrl updated, val=%x", value);
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if ((value & 1) != (this->snd_out_ctrl & 1)) {
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if (value & 1) {
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LOG_F(9, "AMIC Sound Out DMA enabled!");
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this->snd_out_dma->init(this->dma_base & ~0x3FFFF,
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this->snd_buf_size);
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this->snd_out_dma->enable();
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this->awacs->set_sample_rate((this->snd_out_ctrl >> 1) & 3);
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this->awacs->start_output_dma();
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} else {
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LOG_F(9, "AMIC Sound Out DMA disabled!");
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this->snd_out_dma->disable();
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}
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}
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this->snd_out_ctrl = value;
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break;
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case AMICReg::Snd_In_Ctrl:
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LOG_F(INFO, "AMIC Sound In Ctrl updated, val=%x", value);
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break;
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case AMICReg::Snd_Out_DMA:
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this->snd_out_dma->write_dma_out_ctrl(value);
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break;
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case AMICReg::VIA2_Slot_IER:
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case AMICReg::VIA2_Slot_IER:
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LOG_F(INFO, "AMIC VIA2 Slot Interrupt Enable Register updated, val=%x", value);
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LOG_F(INFO, "AMIC VIA2 Slot Interrupt Enable Register updated, val=%x", value);
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break;
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break;
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