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cpu: Add ppc_grab_regssash macro.
This macro is like ppc_grab_regssa but includes rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
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@ -372,8 +372,7 @@ template void dppc_interpreter::power_sleq<RC1>();
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template <field_rc rec>
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template <field_rc rec>
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void dppc_interpreter::power_sliq() {
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void dppc_interpreter::power_sliq() {
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ppc_grab_regssa(ppc_cur_instruction);
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ppc_grab_regssash(ppc_cur_instruction);
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unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
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ppc_result_a = ppc_result_d << rot_sh;
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ppc_result_a = ppc_result_d << rot_sh;
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ppc_state.spr[SPR::MQ] = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
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ppc_state.spr[SPR::MQ] = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
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@ -389,8 +388,7 @@ template void dppc_interpreter::power_sliq<RC1>();
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template <field_rc rec>
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template <field_rc rec>
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void dppc_interpreter::power_slliq() {
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void dppc_interpreter::power_slliq() {
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ppc_grab_regssa(ppc_cur_instruction);
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ppc_grab_regssash(ppc_cur_instruction);
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unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
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uint32_t r = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
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uint32_t r = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
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uint32_t mask = power_rot_mask(0, 31 - rot_sh);
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uint32_t mask = power_rot_mask(0, 31 - rot_sh);
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@ -451,8 +449,7 @@ template void dppc_interpreter::power_slq<RC1>();
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template <field_rc rec>
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template <field_rc rec>
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void dppc_interpreter::power_sraiq() {
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void dppc_interpreter::power_sraiq() {
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ppc_grab_regssa(ppc_cur_instruction);
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ppc_grab_regssash(ppc_cur_instruction);
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unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
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uint32_t mask = (1 << rot_sh) - 1;
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uint32_t mask = (1 << rot_sh) - 1;
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ppc_result_a = (int32_t)ppc_result_d >> rot_sh;
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ppc_result_a = (int32_t)ppc_result_d >> rot_sh;
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ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
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ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
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@ -557,8 +554,7 @@ template void dppc_interpreter::power_sreq<RC1>();
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template <field_rc rec>
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template <field_rc rec>
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void dppc_interpreter::power_sriq() {
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void dppc_interpreter::power_sriq() {
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ppc_grab_regssa(ppc_cur_instruction);
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ppc_grab_regssash(ppc_cur_instruction);
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unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
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ppc_result_a = ppc_result_d >> rot_sh;
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ppc_result_a = ppc_result_d >> rot_sh;
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ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
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ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
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@ -573,8 +569,7 @@ template void dppc_interpreter::power_sriq<RC1>();
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template <field_rc rec>
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template <field_rc rec>
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void dppc_interpreter::power_srliq() {
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void dppc_interpreter::power_srliq() {
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ppc_grab_regssa(ppc_cur_instruction);
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ppc_grab_regssash(ppc_cur_instruction);
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unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
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uint32_t r = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
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uint32_t r = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
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unsigned mask = power_rot_mask(rot_sh, 31);
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unsigned mask = power_rot_mask(rot_sh, 31);
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@ -74,6 +74,12 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
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uint32_t ppc_result_d = ppc_state.gpr[reg_s]; \
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uint32_t ppc_result_d = ppc_state.gpr[reg_s]; \
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uint32_t ppc_result_a = ppc_state.gpr[reg_a];
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uint32_t ppc_result_a = ppc_state.gpr[reg_a];
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#define ppc_grab_regssash(opcode) \
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uint32_t reg_s = (opcode >> 21) & 31; \
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uint32_t reg_a = (opcode >> 16) & 31; \
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uint32_t rot_sh = (opcode >> 11) & 31; \
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uint32_t ppc_result_d = ppc_state.gpr[reg_s]; \
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uint32_t ppc_result_a = ppc_state.gpr[reg_a];
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#define ppc_grab_regssb(opcode) \
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#define ppc_grab_regssb(opcode) \
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uint32_t reg_s = (opcode >> 21) & 31; \
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uint32_t reg_s = (opcode >> 21) & 31; \
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@ -647,16 +647,15 @@ template void dppc_interpreter::ppc_sraw<RC1>();
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template <field_rc rec>
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template <field_rc rec>
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void dppc_interpreter::ppc_srawi() {
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void dppc_interpreter::ppc_srawi() {
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ppc_grab_regssa(ppc_cur_instruction);
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ppc_grab_regssash(ppc_cur_instruction);
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uint32_t shift = (ppc_cur_instruction >> 11) & 0x1F;
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// clear XER[CA] by default
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// clear XER[CA] by default
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ppc_state.spr[SPR::XER] &= ~XER::CA;
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ppc_state.spr[SPR::XER] &= ~XER::CA;
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if ((ppc_result_d & 0x80000000UL) && (ppc_result_d & ((1U << shift) - 1)))
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if ((ppc_result_d & 0x80000000UL) && (ppc_result_d & ((1U << rot_sh) - 1)))
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ppc_state.spr[SPR::XER] |= XER::CA;
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ppc_state.spr[SPR::XER] |= XER::CA;
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ppc_result_a = int32_t(ppc_result_d) >> shift;
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ppc_result_a = int32_t(ppc_result_d) >> rot_sh;
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if (rec)
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if (rec)
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ppc_changecrf0(ppc_result_a);
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ppc_changecrf0(ppc_result_a);
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@ -675,8 +674,7 @@ static inline uint32_t rot_mask(unsigned rot_mb, unsigned rot_me) {
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}
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}
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void dppc_interpreter::ppc_rlwimi() {
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void dppc_interpreter::ppc_rlwimi() {
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ppc_grab_regssa(ppc_cur_instruction);
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ppc_grab_regssash(ppc_cur_instruction);
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unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
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unsigned rot_mb = (ppc_cur_instruction >> 6) & 0x1F;
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unsigned rot_mb = (ppc_cur_instruction >> 6) & 0x1F;
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unsigned rot_me = (ppc_cur_instruction >> 1) & 0x1F;
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unsigned rot_me = (ppc_cur_instruction >> 1) & 0x1F;
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uint32_t mask = rot_mask(rot_mb, rot_me);
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uint32_t mask = rot_mask(rot_mb, rot_me);
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@ -690,8 +688,7 @@ void dppc_interpreter::ppc_rlwimi() {
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}
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}
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void dppc_interpreter::ppc_rlwinm() {
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void dppc_interpreter::ppc_rlwinm() {
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ppc_grab_regssa(ppc_cur_instruction);
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ppc_grab_regssash(ppc_cur_instruction);
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unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
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unsigned rot_mb = (ppc_cur_instruction >> 6) & 0x1F;
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unsigned rot_mb = (ppc_cur_instruction >> 6) & 0x1F;
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unsigned rot_me = (ppc_cur_instruction >> 1) & 0x1F;
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unsigned rot_me = (ppc_cur_instruction >> 1) & 0x1F;
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uint32_t mask = rot_mask(rot_mb, rot_me);
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uint32_t mask = rot_mask(rot_mb, rot_me);
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@ -1820,10 +1817,9 @@ void dppc_interpreter::ppc_stswi() {
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#ifdef CPU_PROFILING
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#ifdef CPU_PROFILING
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num_int_stores++;
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num_int_stores++;
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#endif
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#endif
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ppc_grab_regssa(ppc_cur_instruction);
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ppc_grab_regssash(ppc_cur_instruction);
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ppc_effective_address = reg_a ? ppc_result_a : 0;
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ppc_effective_address = reg_a ? ppc_result_a : 0;
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uint32_t grab_inb = (ppc_cur_instruction >> 11) & 0x1F;
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uint32_t grab_inb = rot_sh ? rot_sh : 32;
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grab_inb = grab_inb ? grab_inb : 32;
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while (grab_inb >= 4) {
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while (grab_inb >= 4) {
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mmu_write_vmem<uint32_t>(ppc_effective_address, ppc_state.gpr[reg_s]);
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mmu_write_vmem<uint32_t>(ppc_effective_address, ppc_state.gpr[reg_s]);
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