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https://github.com/dingusdev/dingusppc.git
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ppcopcodes: set DSISR for alignment exception.
This commit is contained in:
joevt
Maxim Poliakovski
parent
57d919e424
commit
cf4ce01ddd
@ -394,6 +394,7 @@ void update_fpscr(uint32_t new_fpscr);
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void ppc_exception_handler(Except_Type exception_type, uint32_t srr1_bits);
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[[noreturn]] void dbg_exception_handler(Except_Type exception_type, uint32_t srr1_bits);
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void ppc_floating_point_exception();
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void ppc_alignment_exception(uint32_t ea);
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// MEMORY DECLARATIONS
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extern MemCtrlBase* mem_ctrl_instance;
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@ -200,3 +200,115 @@ void ppc_floating_point_exception() {
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ppc_state.pc, ppc_cur_instruction);
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// mmu_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::FPU_EXCEPTION);
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}
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void ppc_alignment_exception(uint32_t ea)
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{
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uint32_t dsisr;
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switch (ppc_cur_instruction & 0xfc000000) {
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case 0x80000000: // lwz
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case 0x90000000: // stw
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case 0xa0000000: // lhz
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case 0xa8000000: // lha
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case 0xb0000000: // sth
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case 0xb8000000: // lmw
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case 0xc0000000: // lfs
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case 0xc8000000: // lfd
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case 0xd0000000: // stfs
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case 0xd8000000: // stfd
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case 0x84000000: // lwzu
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case 0x94000000: // stwu
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case 0xa4000000: // lhzu
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case 0xac000000: // lhau
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case 0xb4000000: // sthu
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case 0xbc000000: // stmw
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case 0xc4000000: // lfsu
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case 0xcc000000: // lfdu
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case 0xd4000000: // stfsu
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case 0xdc000000: // stfdu
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indirect_with_immediate_index:
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dsisr = ((ppc_cur_instruction >> 12) & 0x00004000) // bit 17 — Set to bit 5 of the instruction.
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| ((ppc_cur_instruction >> 17) & 0x00003c00); // bits 18–21 - set to bits 1–4 of the instruction.
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break;
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case 0x7c000000:
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switch (ppc_cur_instruction & 0xfc0007ff) {
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case 0x7c000028: // lwarx (invalid form - bits 15-21 of DSISR are identical to those of lwz)
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case 0x7c0002aa: // lwax (64-bit only)
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case 0x7c00042a: // lswx
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case 0x7c0004aa: // lswi
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case 0x7c00052a: // stswx
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case 0x7c0005aa: // stswi
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case 0x7c0002ea: // lwaux (64 bit only)
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case 0x7c00012c: // stwcx
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case 0x7c00042c: // lwbrx
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case 0x7c00052c: // stwbrx
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case 0x7c00062c: // lhbrx
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case 0x7c00072c: // sthbrx
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case 0x7c00026c: // eciwx // MPC7451
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case 0x7c00036c: // ecowx // MPC7451
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case 0x7c00002e: // lwzx
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case 0x7c00012e: // stwx
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case 0x7c00022e: // lhzx
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case 0x7c0002ae: // lhax
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case 0x7c00032e: // sthx
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case 0x7c00042e: // lfsx
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case 0x7c0004ae: // lfdx
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case 0x7c00052e: // stfsx
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case 0x7c0005ae: // stfdx
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case 0x7c00006e: // lwzux
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case 0x7c00016e: // stwux
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case 0x7c00026e: // lhzux
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case 0x7c0002ee: // lhaux
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case 0x7c00036e: // sthux
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case 0x7c00046e: // lfsux
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case 0x7c0004ee: // lfdux
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case 0x7c00056e: // stfsux
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case 0x7c0005ee: // stfdux
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indirect_with_index:
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dsisr = ((ppc_cur_instruction << 14) & 0x00018000) // bits 15–16 - set to bits 29–30 of the instruction.
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| ((ppc_cur_instruction << 8) & 0x00004000) // bit 17 - set to bit 25 of the instruction.
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| ((ppc_cur_instruction << 3) & 0x00003c00); // bits 18–21 - set to bits 21–24 of the instruction.
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break;
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case 0x7c0007ec:
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if ((ppc_cur_instruction & 0xffe007ff) == 0x7c0007ec) // dcbz
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goto indirect_with_index;
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/* fallthrough */
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default:
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goto unexpected_instruction;
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}
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break;
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default:
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unexpected_instruction:
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dsisr = 0;
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LOG_F(ERROR, "Alignment exception from unexpected instruction 0x%08x",
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ppc_cur_instruction);
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}
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// bits 22–26 - Set to bits 6–10 (source or destination) of the instruction.
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// Undefined for dcbz.
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dsisr |= ((ppc_cur_instruction >> 16) & 0x000003e0);
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if ((ppc_cur_instruction & 0xfc000000) == 0xb8000000) { // lmw
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LOG_F(ERROR, "Alignment exception from instruction 0x%08x (lmw). "
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"What to set DSISR bits 27-31?", ppc_cur_instruction);
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// dsisr |= ((ppc_cur_instruction >> ?) & 0x0000001f); // bits 27–31
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}
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else if ((ppc_cur_instruction & 0xfc0007ff) == 0x7c0004aa) { // lswi
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LOG_F(ERROR, "Alignment exception from instruction 0x%08x (lswi). "
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"What to set DSISR bits 27-31?", ppc_cur_instruction);
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// dsisr |= ((ppc_cur_instruction >> ?) & 0x0000001f); // bits 27–31
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}
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else if ((ppc_cur_instruction & 0xfc0007ff) == 0x7c00042a) { // lswx
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LOG_F(ERROR, "Alignment exception from instruction 0x%08x (lswx). "
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"What to set DSISR bits 27-31?", ppc_cur_instruction);
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// dsisr |= ((ppc_cur_instruction >> ?) & 0x0000001f); // bits 27–31
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}
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else {
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// bits 27–31 - Set to bits 11–15 of the instruction (rA)
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dsisr |= ((ppc_cur_instruction >> 16) & 0x0000001f);
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}
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ppc_state.spr[SPR::DSISR] = dsisr;
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ppc_state.spr[SPR::DAR] = ea;
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ppc_exception_handler(Except_Type::EXC_ALIGNMENT, 0x0);
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}
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@ -1075,19 +1075,17 @@ inline T mmu_read_vmem(uint32_t guest_va)
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iomem_reads_total++;
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#endif
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if (sizeof(T) == 8) {
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if (guest_va & 3) {
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ppc_exception_handler(Except_Type::EXC_ALIGNMENT, 0x0);
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}
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{
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return (
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((T)tlb2_entry->rgn_desc->devobj->read(tlb2_entry->rgn_desc->start,
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guest_va - tlb2_entry->dev_base_va,
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4) << 32) |
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tlb2_entry->rgn_desc->devobj->read(tlb2_entry->rgn_desc->start,
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guest_va + 4 - tlb2_entry->dev_base_va,
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4)
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);
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}
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if (guest_va & 3)
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ppc_alignment_exception(guest_va);
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return (
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((T)tlb2_entry->rgn_desc->devobj->read(tlb2_entry->rgn_desc->start,
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guest_va - tlb2_entry->dev_base_va,
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4) << 32) |
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tlb2_entry->rgn_desc->devobj->read(tlb2_entry->rgn_desc->start,
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guest_va + 4 - tlb2_entry->dev_base_va,
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4)
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);
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}
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else {
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return (
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@ -1199,19 +1197,16 @@ inline void mmu_write_vmem(uint32_t guest_va, T value)
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iomem_writes_total++;
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#endif
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if (sizeof(T) == 8) {
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if (guest_va & 3) {
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ppc_exception_handler(Except_Type::EXC_ALIGNMENT, 0x0);
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}
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{
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tlb2_entry->rgn_desc->devobj->write(tlb2_entry->rgn_desc->start,
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guest_va - tlb2_entry->dev_base_va,
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value >> 32, 4);
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tlb2_entry->rgn_desc->devobj->write(tlb2_entry->rgn_desc->start,
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guest_va + 4 - tlb2_entry->dev_base_va,
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(uint32_t)value, 4);
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}
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}
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else {
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if (guest_va & 3)
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ppc_alignment_exception(guest_va);
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tlb2_entry->rgn_desc->devobj->write(tlb2_entry->rgn_desc->start,
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guest_va - tlb2_entry->dev_base_va,
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value >> 32, 4);
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tlb2_entry->rgn_desc->devobj->write(tlb2_entry->rgn_desc->start,
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guest_va + 4 - tlb2_entry->dev_base_va,
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(uint32_t)value, 4);
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} else {
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tlb2_entry->rgn_desc->devobj->write(tlb2_entry->rgn_desc->start,
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guest_va - tlb2_entry->dev_base_va,
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value, sizeof(T));
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@ -1282,7 +1277,7 @@ static T read_unaligned(uint32_t guest_va, uint8_t *host_va)
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return READ_DWORD_BE_U(host_va);
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case 8:
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if (guest_va & 3) {
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ppc_exception_handler(Except_Type::EXC_ALIGNMENT, 0x0);
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ppc_alignment_exception(guest_va);
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}
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return READ_QWORD_BE_U(host_va);
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}
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@ -1328,7 +1323,7 @@ static void write_unaligned(uint32_t guest_va, uint8_t *host_va, T value)
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break;
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case 8:
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if (guest_va & 3) {
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ppc_exception_handler(Except_Type::EXC_ALIGNMENT, 0x0);
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ppc_alignment_exception(guest_va);
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}
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WRITE_QWORD_BE_U(host_va, value);
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break;
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@ -1776,7 +1776,7 @@ void dppc_interpreter::ppc_stmw() {
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/* what should we do if EA is unaligned? */
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if (ppc_effective_address & 3) {
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ppc_exception_handler(Except_Type::EXC_ALIGNMENT, 0x00000);
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ppc_alignment_exception(ppc_effective_address);
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}
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for (; reg_s <= 31; reg_s++) {
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@ -2236,7 +2236,7 @@ void dppc_interpreter::ppc_eciwx() {
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ppc_effective_address = (reg_a == 0) ? ppc_result_b : (ppc_result_a + ppc_result_b);
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if (ppc_effective_address & 0x3) {
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ppc_exception_handler(Except_Type::EXC_ALIGNMENT, 0x0);
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ppc_alignment_exception(ppc_effective_address);
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}
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ppc_result_d = mmu_read_vmem<uint32_t>(ppc_effective_address);
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@ -2256,7 +2256,7 @@ void dppc_interpreter::ppc_ecowx() {
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ppc_effective_address = (reg_a == 0) ? ppc_result_b : (ppc_result_a + ppc_result_b);
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if (ppc_effective_address & 0x3) {
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ppc_exception_handler(Except_Type::EXC_ALIGNMENT, 0x0);
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ppc_alignment_exception(ppc_effective_address);
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}
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mmu_write_vmem<uint32_t>(ppc_effective_address, ppc_result_d);
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