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CRx_bit enum stores masks for now.

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This commit is contained in:
Maxim Poliakovski 2023-12-19 14:26:51 +01:00
parent 9dbfde1a4c
commit d24b5d21b8
2 changed files with 15 additions and 12 deletions
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11
cpu/ppc/ppcemu.h
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@ -231,11 +231,14 @@ enum CR_select : int32_t {
CR1_field = (0xF << 24),
};
// Define bit masks for CR0.
// To use them in other CR fields, just right shift it by 4*CR_num bits.
enum CRx_bit : uint32_t {
CR_SO = 28,
CR_EQ = 29,
CR_GT = 30,
CR_LT = 31 };
CR_SO = 1UL << 28,
CR_EQ = 1UL << 29,
CR_GT = 1UL << 30,
CR_LT = 1UL << 31
};
enum CR1_bit : uint32_t {
CR1_OX = 24,

16
cpu/ppc/ppcfpopcodes.cpp
View File

@ -943,16 +943,16 @@ void dppc_interpreter::ppc_fcmpo() {
// TODO: test for SNAN operands
// for now, assume that at least one of the operands is QNAN
ppc_state.fpscr |= FPSCR::VXVC;
cmp_c |= (1 << CRx_bit::CR_SO);
cmp_c |= CRx_bit::CR_SO;
}
else if (db_test_a < db_test_b) {
cmp_c |= (1 << CRx_bit::CR_LT);
cmp_c |= CRx_bit::CR_LT;
}
else if (db_test_a > db_test_b) {
cmp_c |= (1 << CRx_bit::CR_GT);
cmp_c |= CRx_bit::CR_GT;
}
else {
cmp_c |= (1 << CRx_bit::CR_EQ);
cmp_c |= CRx_bit::CR_EQ;
}
ppc_state.fpscr = (ppc_state.fpscr & ~FPSCR::FPCC_MASK) | (cmp_c >> 16); // update FPCC
@ -966,16 +966,16 @@ void dppc_interpreter::ppc_fcmpu() {
if (std::isnan(db_test_a) || std::isnan(db_test_b)) {
// TODO: test for SNAN operands
cmp_c |= (1 << CRx_bit::CR_SO);
cmp_c |= CRx_bit::CR_SO;
}
else if (db_test_a < db_test_b) {
cmp_c |= (1 << CRx_bit::CR_LT);
cmp_c |= CRx_bit::CR_LT;
}
else if (db_test_a > db_test_b) {
cmp_c |= (1 << CRx_bit::CR_GT);
cmp_c |= CRx_bit::CR_GT;
}
else {
cmp_c |= (1 << CRx_bit::CR_EQ);
cmp_c |= CRx_bit::CR_EQ;
}
ppc_state.fpscr = (ppc_state.fpscr & ~FPSCR::FPCC_MASK) | (cmp_c >> 16); // update FPCC