diff --git a/cpu/ppc/ppcemu.h b/cpu/ppc/ppcemu.h
index 63e72c9..ca32a4f 100644
--- a/cpu/ppc/ppcemu.h
+++ b/cpu/ppc/ppcemu.h
@@ -231,11 +231,14 @@ enum CR_select : int32_t {
     CR1_field = (0xF << 24),
 };
 
+// Define bit masks for CR0.
+// To use them in other CR fields, just right shift it by 4*CR_num bits.
 enum CRx_bit : uint32_t {
-    CR_SO = 28,
-    CR_EQ = 29,
-    CR_GT = 30,
-    CR_LT = 31 };
+    CR_SO = 1UL << 28,
+    CR_EQ = 1UL << 29,
+    CR_GT = 1UL << 30,
+    CR_LT = 1UL << 31
+};
 
 enum CR1_bit : uint32_t {
     CR1_OX = 24,
diff --git a/cpu/ppc/ppcfpopcodes.cpp b/cpu/ppc/ppcfpopcodes.cpp
index 597c2df..fc28364 100644
--- a/cpu/ppc/ppcfpopcodes.cpp
+++ b/cpu/ppc/ppcfpopcodes.cpp
@@ -943,16 +943,16 @@ void dppc_interpreter::ppc_fcmpo() {
         // TODO: test for SNAN operands
         // for now, assume that at least one of the operands is QNAN
         ppc_state.fpscr |= FPSCR::VXVC;
-        cmp_c |= (1 << CRx_bit::CR_SO);
+        cmp_c |= CRx_bit::CR_SO;
     }
     else if (db_test_a < db_test_b) {
-        cmp_c |= (1 << CRx_bit::CR_LT);
+        cmp_c |= CRx_bit::CR_LT;
     }
     else if (db_test_a > db_test_b) {
-        cmp_c |= (1 << CRx_bit::CR_GT);
+        cmp_c |= CRx_bit::CR_GT;
     }
     else {
-        cmp_c |= (1 << CRx_bit::CR_EQ);
+        cmp_c |= CRx_bit::CR_EQ;
     }
 
     ppc_state.fpscr = (ppc_state.fpscr & ~FPSCR::FPCC_MASK) | (cmp_c >> 16); // update FPCC
@@ -966,16 +966,16 @@ void dppc_interpreter::ppc_fcmpu() {
 
     if (std::isnan(db_test_a) || std::isnan(db_test_b)) {
         // TODO: test for SNAN operands
-        cmp_c |= (1 << CRx_bit::CR_SO);
+        cmp_c |= CRx_bit::CR_SO;
     }
     else if (db_test_a < db_test_b) {
-        cmp_c |= (1 << CRx_bit::CR_LT);
+        cmp_c |= CRx_bit::CR_LT;
     }
     else if (db_test_a > db_test_b) {
-        cmp_c |= (1 << CRx_bit::CR_GT);
+        cmp_c |= CRx_bit::CR_GT;
     }
     else {
-        cmp_c |= (1 << CRx_bit::CR_EQ);
+        cmp_c |= CRx_bit::CR_EQ;
     }
 
     ppc_state.fpscr = (ppc_state.fpscr & ~FPSCR::FPCC_MASK) | (cmp_c >> 16); // update FPCC