mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-07-02 23:29:37 +00:00
Initial code for the NuInterpreter.
This commit is contained in:
Maxim Poliakovski
parent
6124dfd897
commit
d659253f91
127
cpu/ppc/interpops.h
Normal file
127
cpu/ppc/interpops.h
Normal file
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@ -0,0 +1,127 @@
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GEN_OP(addi, {
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ppc_state.gpr[code->d1] = ppc_state.gpr[code->d2] + code->simm;
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NEXT;
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})
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GEN_OP(adde, {
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uint32_t xer_ca = !!(ppc_state.spr[SPR::XER] & 0x20000000);
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uint32_t val_a = ppc_state.gpr[code->d2];
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uint32_t val_b = ppc_state.gpr[code->d3];
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uint32_t result = val_a + val_b + xer_ca;
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if ((result < val_a) || (xer_ca && (result == val_a))) {
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ppc_state.spr[SPR::XER] |= 0x20000000UL;
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} else {
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ppc_state.spr[SPR::XER] &= 0xDFFFFFFFUL;
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}
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ppc_state.gpr[code->d1] = result;
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NEXT;
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})
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GEN_OP(addze, {
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uint32_t val_a = ppc_state.gpr[code->d2];
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uint32_t xer_ca = !!(ppc_state.spr[SPR::XER] & 0x20000000);
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uint32_t result = val_a + xer_ca;
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if (result < val_a) {
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ppc_state.spr[SPR::XER] |= 0x20000000UL;
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} else {
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ppc_state.spr[SPR::XER] &= 0xDFFFFFFFUL;
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}
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ppc_state.gpr[code->d1] = result;
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NEXT;
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})
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GEN_OP(andidot, {
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uint32_t result = ppc_state.gpr[code->d1] & code->uimm;
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ppc_state.gpr[code->d2] = result;
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ppc_changecrf0(result);
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NEXT;
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})
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GEN_OP(lwz, {
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ppc_state.gpr[code->d1] = (mem_grab_dword((
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(code->d2) ? ppc_state.gpr[code->d2] : 0) + code->simm));
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NEXT;
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})
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GEN_OP(lwzu, {
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uint32_t ea = ppc_state.gpr[code->d2] + code->simm;
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ppc_state.gpr[code->d1] = mem_grab_dword(ea);
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ppc_state.gpr[code->d2] = ea;
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NEXT;
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})
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GEN_OP(lbz, {
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ppc_state.gpr[code->d1] = (mem_grab_byte((
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(code->d2) ? ppc_state.gpr[code->d2] : 0) + code->simm));
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NEXT;
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})
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GEN_OP(lhz, {
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ppc_state.gpr[code->d1] = (mem_grab_word((
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(code->d2) ? ppc_state.gpr[code->d2] : 0) + code->simm));
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NEXT;
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})
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GEN_OP(rlwinm, {
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uint32_t val_s = ppc_state.gpr[code->d1];
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uint32_t r = ((val_s << code->d3) | (val_s >> (32 - code->d3)));
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uint32_t result = r & code->uimm;
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ppc_state.gpr[code->d2] = result;
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if (code->d4) {
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ppc_changecrf0(result);
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}
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NEXT;
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})
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GEN_OP(srawidot, {
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uint32_t val_s = ppc_state.gpr[code->d1];
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uint32_t result = (int32_t)val_s >> code->d2;
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if ((val_s & 0x80000000UL) && (val_s & code->uimm)) {
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ppc_state.spr[SPR::XER] |= 0x20000000UL;
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} else {
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ppc_state.spr[SPR::XER] &= 0xDFFFFFFFUL;
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}
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ppc_state.gpr[code->d2] = result;
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ppc_changecrf0(result);
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NEXT;
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})
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GEN_OP(bc, {
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if (ppc_state.cr & code->uimm) {
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interp_tpc += code->bt;
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} else {
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NEXT;
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}
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})
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GEN_OP(mtspr, {
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ppc_state.spr[code->uimm] = ppc_state.gpr[code->d1];
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NEXT;
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})
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GEN_OP(bdnz, {
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if (--ppc_state.spr[SPR::CTR]) {
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interp_tpc += code->bt;
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} else {
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NEXT;
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}
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})
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GEN_OP(bdz, {
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if (!(--ppc_state.spr[SPR::CTR])) {
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interp_tpc += code->bt;
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} else {
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NEXT;
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}
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})
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GEN_OP(bclr, {
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// PLACEHOLDER
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})
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GEN_OP(bexit, {
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ppc_state.pc = code->uimm; // write source pc
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interp_running = false;
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})
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185
cpu/ppc/jittables.cpp
Normal file
185
cpu/ppc/jittables.cpp
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@ -0,0 +1,185 @@
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#include <cinttypes>
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#include <map>
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#include "jittables.h"
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#include "ppcdefs.h"
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uint16_t main_index_tab[64] = {
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PPCInstr::illegal, PPCInstr::illegal, PPCInstr::illegal,
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PPCInstr::twi, PPCInstr::illegal, PPCInstr::illegal,
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PPCInstr::illegal, PPCInstr::mulli, PPCInstr::subfic,
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PPCInstr::dozi, PPCInstr::cmpli, PPCInstr::cmpi,
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PPCInstr::addic, PPCInstr::addicdot, PPCInstr::addi,
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PPCInstr::addis, PPCInstr::illegal, PPCInstr::sc,
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PPCInstr::illegal, PPCInstr::illegal, PPCInstr::rlwimix,
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PPCInstr::rlwinmx, PPCInstr::rlmi, PPCInstr::rlwnmx,
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PPCInstr::ori, PPCInstr::oris, PPCInstr::xori,
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PPCInstr::xoris, PPCInstr::andidot, PPCInstr::andisdot,
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PPCInstr::illegal, PPCInstr::illegal, PPCInstr::lwz,
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PPCInstr::lwzu, PPCInstr::lbz, PPCInstr::lbzu,
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PPCInstr::stw, PPCInstr::stwu, PPCInstr::stb,
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PPCInstr::stbu, PPCInstr::lhz, PPCInstr::lhzu,
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PPCInstr::lha, PPCInstr::lhau, PPCInstr::sth,
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PPCInstr::sthu, PPCInstr::lmw, PPCInstr::stmw,
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PPCInstr::lfs, PPCInstr::lfsu, PPCInstr::lfd,
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PPCInstr::lfdu, PPCInstr::stfs, PPCInstr::stfsu,
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PPCInstr::stfd, PPCInstr::stfdu, PPCInstr::illegal,
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PPCInstr::illegal, PPCInstr::illegal, PPCInstr::illegal,
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PPCInstr::illegal, PPCInstr::illegal, PPCInstr::illegal,
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PPCInstr::illegal
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};
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uint16_t subgrp16_index_tab[4] = {
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PPCInstr::bc, PPCInstr::bcl, PPCInstr::bca, PPCInstr::bcla
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};
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uint16_t subgrp18_index_tab[4] = {
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PPCInstr::b, PPCInstr::bl, PPCInstr::ba, PPCInstr::bla
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};
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uint16_t subgrp19_index_tab[2048] = { PPCInstr::illegal };
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uint16_t subgrp31_index_tab[2048] = { PPCInstr::illegal };
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uint16_t subgrp59_index_tab[64] = { PPCInstr::illegal };
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uint16_t subgrp63_index_tab[2048] = { PPCInstr::illegal };
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static std::map<uint16_t, PPCInstr> Subop19Init = {
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{ 32, PPCInstr::bclr },
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{ 33, PPCInstr::bclrl },
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{ 66, PPCInstr::crnor },
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{ 100, PPCInstr::rfi },
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{ 258, PPCInstr::crandc },
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{ 300, PPCInstr::isync },
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{ 386, PPCInstr::crxor },
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{ 450, PPCInstr::crnand },
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{ 514, PPCInstr::crand },
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{ 578, PPCInstr::creqv },
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{ 834, PPCInstr::crorc },
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{ 898, PPCInstr::cror },
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{ 1056, PPCInstr::bcctr },
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{ 1057, PPCInstr::bcctrl }
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};
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static std::map<uint16_t, PPCInstr> Subop31Init = {
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{ 0, PPCInstr::cmp}, { 8, PPCInstr::tw},
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{ 16, PPCInstr::subfc}, { 17, PPCInstr::subfcdot},
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{ 20, PPCInstr::addc}, { 21, PPCInstr::addcdot},
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{ 22, PPCInstr::mulhwu}, { 23, PPCInstr::mulhwudot},
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{ 38, PPCInstr::mfcr}, { 40, PPCInstr::lwarx},
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{ 46, PPCInstr::lwzx}, { 48, PPCInstr::slw},
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{ 49, PPCInstr::slwdot}, { 52, PPCInstr::cntlzw},
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{ 53, PPCInstr::cntlzwdot}, { 56, PPCInstr::ppc_and},
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{ 57, PPCInstr::anddot}, { 58, PPCInstr::maskg},
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{ 59, PPCInstr::maskgdot}, { 64, PPCInstr::cmpl},
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{ 80, PPCInstr::subf}, { 81, PPCInstr::subfdot},
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{ 108, PPCInstr::dcbst}, { 110, PPCInstr::lwzux},
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{ 120, PPCInstr::andc}, { 121, PPCInstr::andcdot},
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{ 150, PPCInstr::mulhw}, { 151, PPCInstr::mulhwdot},
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{ 166, PPCInstr::mfmsr}, { 172, PPCInstr::dcbf},
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{ 174, PPCInstr::lbzx}, { 208, PPCInstr::neg},
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{ 209, PPCInstr::negdot}, { 214, PPCInstr::mul},
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{ 215, PPCInstr::muldot}, { 238, PPCInstr::lbzux},
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{ 248, PPCInstr::nor}, { 249, PPCInstr::nordot},
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{ 272, PPCInstr::subfe}, { 273, PPCInstr::subfedot},
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{ 276, PPCInstr::adde}, { 277, PPCInstr::addedot},
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{ 288, PPCInstr::mtcrf}, { 292, PPCInstr::mtmsr},
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{ 301, PPCInstr::stwcx}, { 302, PPCInstr::stwx},
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{ 304, PPCInstr::slq}, { 305, PPCInstr::slqdot},
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{ 306, PPCInstr::sle}, { 307, PPCInstr::sledot},
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{ 366, PPCInstr::stwux}, { 368, PPCInstr::sliq},
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{ 400, PPCInstr::subfze}, { 401, PPCInstr::subfzedot},
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{ 404, PPCInstr::addze}, { 405, PPCInstr::addzedot},
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{ 420, PPCInstr::mtsr}, { 430, PPCInstr::stbx},
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{ 432, PPCInstr::sllq}, { 433, PPCInstr::sllqdot},
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{ 434, PPCInstr::sleq}, { 436, PPCInstr::sleqdot},
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{ 464, PPCInstr::subfme}, { 465, PPCInstr::subfmedot},
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{ 468, PPCInstr::addme}, { 469, PPCInstr::addmedot},
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{ 470, PPCInstr::mullw}, { 471, PPCInstr::mullwdot},
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{ 484, PPCInstr::mtsrin}, { 492, PPCInstr::dcbtst},
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{ 494, PPCInstr::stbux}, { 496, PPCInstr::slliq},
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{ 497, PPCInstr::slliqdot}, { 528, PPCInstr::doz},
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{ 529, PPCInstr::dozdot}, { 532, PPCInstr::add},
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{ 533, PPCInstr::adddot}, { 554, PPCInstr::lscbx},
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{ 555, PPCInstr::lscbxdot}, { 556, PPCInstr::dcbt},
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{ 558, PPCInstr::lhzx}, { 568, PPCInstr::eqv},
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{ 569, PPCInstr::eqvdot}, { 612, PPCInstr::tlbie},
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{ 622, PPCInstr::lhzux}, { 632, PPCInstr::ppc_xor},
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{ 633, PPCInstr::xordot}, { 662, PPCInstr::div},
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{ 663, PPCInstr::divdot}, { 678, PPCInstr::mfspr},
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{ 686, PPCInstr::lhax}, { 720, PPCInstr::abs},
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{ 721, PPCInstr::absdot}, { 726, PPCInstr::divs},
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{ 727, PPCInstr::divsdot}, { 740, PPCInstr::tlbia},
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{ 742, PPCInstr::mftb}, { 750, PPCInstr::lhaux},
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{ 814, PPCInstr::sthx}, { 824, PPCInstr::orc},
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{ 825, PPCInstr::orcdot}, { 878, PPCInstr::sthux},
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{ 888, PPCInstr::ppc_or}, { 889, PPCInstr::ordot},
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{ 918, PPCInstr::divwu}, { 919, PPCInstr::divwudot},
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{ 934, PPCInstr::mtspr}, { 940, PPCInstr::dcbi},
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{ 952, PPCInstr::nand}, { 953, PPCInstr::nanddot},
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{ 976, PPCInstr::nabs}, { 977, PPCInstr::nabsdot},
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{ 982, PPCInstr::divw}, { 983, PPCInstr::divwdot},
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{ 1024, PPCInstr::mcrxr}, { 1040, PPCInstr::subfco},
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{ 1041, PPCInstr::subfcodot}, { 1044, PPCInstr::addco},
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{ 1045, PPCInstr::addcodot}, { 1062, PPCInstr::clcs},
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{ 1063, PPCInstr::clcsdot}, { 1066, PPCInstr::lswx},
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{ 1068, PPCInstr::lwbrx}, { 1070, PPCInstr::lfsx},
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{ 1072, PPCInstr::srw}, { 1073, PPCInstr::srwdot},
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{ 1074, PPCInstr::rrib}, { 1075, PPCInstr::rribdot},
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{ 1082, PPCInstr::maskir}, { 1083, PPCInstr::maskirdot},
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{ 1104, PPCInstr::subfo}, { 1105, PPCInstr::subfodot},
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{ 1132, PPCInstr::tlbsync}, { 1134, PPCInstr::lfsux},
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{ 1190, PPCInstr::mfsr}, { 1194, PPCInstr::lswi},
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{ 1196, PPCInstr::sync}, { 1198, PPCInstr::lfdx},
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{ 1232, PPCInstr::nego}, { 1233, PPCInstr::negodot},
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{ 1238, PPCInstr::mulo}, { 1239, PPCInstr::mulodot},
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{ 1262, PPCInstr::lfdux}, { 1296, PPCInstr::subfeo},
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{ 1297, PPCInstr::subfeodot}, { 1300, PPCInstr::addeo},
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{ 1301, PPCInstr::addeodot}, { 1318, PPCInstr::mfsrin},
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{ 1322, PPCInstr::stswx}, { 1324, PPCInstr::stwbrx},
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{ 1326, PPCInstr::stfsx}, { 1328, PPCInstr::srq},
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{ 1329, PPCInstr::srqdot}, { 1330, PPCInstr::sre},
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{ 1331, PPCInstr::sredot}, { 1390, PPCInstr::stfsux},
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{ 1392, PPCInstr::sriq}, { 1393, PPCInstr::sriqdot},
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{ 1424, PPCInstr::subfzeo}, { 1425, PPCInstr::subfzeodot},
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{ 1428, PPCInstr::addzeo}, { 1429, PPCInstr::addzeodot},
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{ 1450, PPCInstr::stswi}, { 1454, PPCInstr::stfdx},
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{ 1456, PPCInstr::srlq}, { 1457, PPCInstr::srlqdot},
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{ 1458, PPCInstr::sreq }, { 1459, PPCInstr::sreqdot},
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{ 1488, PPCInstr::subfmeo }, { 1489, PPCInstr::subfmeodot},
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{ 1492, PPCInstr::addmeo }, { 1493, PPCInstr::addmeodot},
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{ 1494, PPCInstr::mullwo }, { 1495, PPCInstr::mullwodot},
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{ 1518, PPCInstr::stfdux }, { 1520, PPCInstr::srliq},
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{ 1521, PPCInstr::srliqdot }, { 1552, PPCInstr::dozo},
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{ 1553, PPCInstr::dozodot }, { 1556, PPCInstr::addo},
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{ 1557, PPCInstr::addodot }, { 1580, PPCInstr::lhbrx},
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{ 1584, PPCInstr::sraw }, { 1585, PPCInstr::srawdot},
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{ 1648, PPCInstr::srawi }, { 1649, PPCInstr::srawidot},
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{ 1686, PPCInstr::divo }, { 1687, PPCInstr::divodot},
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{ 1708, PPCInstr::eieio }, { 1744, PPCInstr::abso},
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{ 1745, PPCInstr::absodot }, { 1750, PPCInstr::divso},
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{ 1751, PPCInstr::divsodot }, { 1836, PPCInstr::sthbrx},
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{ 1840, PPCInstr::sraq }, { 1841, PPCInstr::sraqdot},
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{ 1842, PPCInstr::srea }, { 1843, PPCInstr::sreadot},
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{ 1844, PPCInstr::extsh }, { 1845, PPCInstr::extshdot},
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{ 1904, PPCInstr::sraiq }, { 1905, PPCInstr::sraiqdot},
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{ 1908, PPCInstr::extsb }, { 1909, PPCInstr::extsbdot},
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{ 1942, PPCInstr::divwuo }, { 1943, PPCInstr::divwuodot},
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{ 1956, PPCInstr::tlbld }, { 1964, PPCInstr::icbi},
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{ 1966, PPCInstr::stfiwx }, { 2000, PPCInstr::nabso},
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{ 2001, PPCInstr::nabsodot }, { 2006, PPCInstr::divwo},
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{ 2007, PPCInstr::divwodot }, { 2020, PPCInstr::tlbli},
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{ 2028, PPCInstr::dcbz }
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};
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void init_jit_tables() {
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std::map<uint16_t, PPCInstr>::iterator it;
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for (it = Subop19Init.begin(); it != Subop19Init.end(); it++ ) {
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subgrp19_index_tab[it->first] = it->second;
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}
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for (it = Subop31Init.begin(); it != Subop31Init.end(); it++ ) {
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subgrp31_index_tab[it->first] = it->second;
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}
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}
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48
cpu/ppc/jittables.h
Normal file
48
cpu/ppc/jittables.h
Normal file
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@ -0,0 +1,48 @@
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#ifndef JIT_TABLES_H
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#define JIT_TABLES_H
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#include <cinttypes>
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#include "ppcemu.h"
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/** Instruction operands formats. */
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enum class InstrOps {
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opNone,
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opDA,
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opDAB,
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opDASimm,
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opSAUimm,
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opSASh,
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opRot,
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opSSpr,
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opBrRel,
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opBrLink,
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};
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/* Control flow kind. */
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enum class CFlowType {
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CFL_NONE,
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CFL_COND_BRANCH,
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CFL_UNCOND_BRANCH,
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CFL_TRAP,
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};
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struct InstrInfo {
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InstrOps ops_fmt; // describes operands format
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CFlowType cflow_type; // control flow type
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int num_cycles;
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// Required by JIT
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//int flags; // flags updated by this instruction
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};
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extern uint16_t main_index_tab[];
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extern uint16_t subgrp16_index_tab[];
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extern uint16_t subgrp18_index_tab[];
|
||||
extern uint16_t subgrp19_index_tab[];
|
||||
extern uint16_t subgrp31_index_tab[];
|
||||
extern uint16_t subgrp59_index_tab[];
|
||||
extern uint16_t subgrp63_index_tab[];
|
||||
|
||||
void init_jit_tables(void);
|
||||
|
||||
#endif /* JIT_TABLES_H */
|
||||
238
cpu/ppc/nuinterpreter.cpp
Normal file
238
cpu/ppc/nuinterpreter.cpp
Normal file
|
|
@ -0,0 +1,238 @@
|
|||
#include <cinttypes>
|
||||
#include <thirdparty/loguru/loguru.hpp>
|
||||
#include "ppcemu.h"
|
||||
#include "ppcmmu.h"
|
||||
#include "ppcdefs.h"
|
||||
#include "jittables.h"
|
||||
|
||||
struct CachedInstr; // forward declaration
|
||||
|
||||
typedef void (*ImplSubr)(const CachedInstr *);
|
||||
|
||||
struct CachedInstr {
|
||||
ImplSubr call_me;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint8_t d1;
|
||||
uint8_t d2;
|
||||
uint8_t d3;
|
||||
uint8_t d4;
|
||||
};
|
||||
int32_t bt; // branch target
|
||||
};
|
||||
|
||||
union {
|
||||
int32_t simm;
|
||||
uint32_t uimm;
|
||||
};
|
||||
};
|
||||
|
||||
CachedInstr* interp_tpc;
|
||||
bool interp_running;
|
||||
|
||||
#define GEN_OP(name,body) void impl_##name(const CachedInstr* code) {body}
|
||||
#define NEXT interp_tpc++
|
||||
|
||||
#include "interpops.h"
|
||||
|
||||
struct InterpInstr {
|
||||
ImplSubr emu_fn; // pointer to the instruction emulation routine
|
||||
InstrInfo info;
|
||||
};
|
||||
|
||||
/* WARNING: entries in this table MUST be in the same order as constants in PPCInstr! */
|
||||
InterpInstr interp_tab[] = {
|
||||
{nullptr, {InstrOps::opNone, CFlowType::CFL_NONE, 0}},
|
||||
{impl_addi, {InstrOps::opDASimm, CFlowType::CFL_NONE, 1}},
|
||||
{impl_adde, {InstrOps::opDAB, CFlowType::CFL_NONE, 1}},
|
||||
{impl_addze, {InstrOps::opDA, CFlowType::CFL_NONE, 1}},
|
||||
{impl_andidot, {InstrOps::opSAUimm, CFlowType::CFL_NONE, 1}},
|
||||
{impl_lwz, {InstrOps::opDASimm, CFlowType::CFL_NONE, 1}},
|
||||
{impl_lwzu, {InstrOps::opDASimm, CFlowType::CFL_NONE, 1}},
|
||||
{impl_lbz, {InstrOps::opDASimm, CFlowType::CFL_NONE, 1}},
|
||||
{impl_lhz, {InstrOps::opDASimm, CFlowType::CFL_NONE, 1}},
|
||||
{impl_rlwinm, {InstrOps::opRot, CFlowType::CFL_NONE, 1}},
|
||||
{impl_srawidot, {InstrOps::opSASh, CFlowType::CFL_NONE, 1}},
|
||||
{impl_bc, {InstrOps::opBrRel, CFlowType::CFL_COND_BRANCH, 0}},
|
||||
{impl_bdnz, {InstrOps::opBrRel, CFlowType::CFL_COND_BRANCH, 0}},
|
||||
{impl_bdz, {InstrOps::opBrRel, CFlowType::CFL_COND_BRANCH, 0}},
|
||||
{impl_bclr, {InstrOps::opBrLink, CFlowType::CFL_COND_BRANCH, 0}},
|
||||
{impl_mtspr, {InstrOps::opSSpr, CFlowType::CFL_NONE, 2}},
|
||||
{impl_bexit, {InstrOps::opNone, CFlowType::CFL_UNCOND_BRANCH, 0}},
|
||||
};
|
||||
|
||||
CachedInstr code_block[256];
|
||||
|
||||
#define REG_D(opcode) ((opcode >> 21) & 0x1F)
|
||||
#define REG_A(opcode) ((opcode >> 16) & 0x1F)
|
||||
#define REG_B(opcode) ((opcode >> 11) & 0x1F)
|
||||
#define REG_S REG_D
|
||||
#define BR_BO REG_D
|
||||
#define BR_BI REG_A
|
||||
#define SIMM(opcode) ((int32_t)((int16_t)(opcode & 0xFFFF)))
|
||||
#define UIMM(opcode) ((uint32_t)((uint16_t)(opcode & 0xFFFF)))
|
||||
|
||||
/** mask generator for rotate and shift instructions (§ 4.2.1.4 PowerpC PEM) */
|
||||
static inline uint32_t rot_mask(unsigned rot_mb, unsigned rot_me) {
|
||||
uint32_t m1 = 0xFFFFFFFFUL >> rot_mb;
|
||||
uint32_t m2 = 0xFFFFFFFFUL << (31 - rot_me);
|
||||
return ((rot_mb <= rot_me) ? m2 & m1 : m1 | m2);
|
||||
}
|
||||
|
||||
|
||||
bool PreDecode(uint32_t next_pc, CachedInstr* c_instr)
|
||||
{
|
||||
uint32_t opcode, main_opcode;
|
||||
unsigned instr_index;
|
||||
uint8_t* pc_real;
|
||||
bool done;
|
||||
|
||||
pc_real = quickinstruction_translate(next_pc);
|
||||
|
||||
//CachedInstr* c_instr = &code[0];
|
||||
|
||||
done = false;
|
||||
|
||||
while (!done) {
|
||||
opcode = ppc_cur_instruction;
|
||||
main_opcode = opcode >> 26;
|
||||
|
||||
instr_index = main_index_tab[main_opcode];
|
||||
if (!instr_index) {
|
||||
switch (main_opcode) {
|
||||
case 16:
|
||||
instr_index = subgrp16_index_tab[opcode & 3];
|
||||
break;
|
||||
case 18:
|
||||
instr_index = subgrp18_index_tab[opcode & 3];
|
||||
break;
|
||||
case 19:
|
||||
instr_index = subgrp19_index_tab[opcode & 0x7FF];
|
||||
break;
|
||||
case 31:
|
||||
instr_index = subgrp31_index_tab[opcode & 0x7FF];
|
||||
break;
|
||||
case 59:
|
||||
instr_index = subgrp59_index_tab[opcode & 0x3F];
|
||||
break;
|
||||
case 63:
|
||||
instr_index = subgrp63_index_tab[opcode & 0x7FF];
|
||||
break;
|
||||
default:
|
||||
instr_index = 0;
|
||||
}
|
||||
|
||||
if (!instr_index) {
|
||||
LOG_F(ERROR, "Illegal opcode 0x%08X - Program exception!", opcode);
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
const InterpInstr* p_instr = &interp_tab[instr_index];
|
||||
|
||||
c_instr->call_me = p_instr->emu_fn;
|
||||
|
||||
if (p_instr->info.cflow_type == CFlowType::CFL_UNCOND_BRANCH) {
|
||||
// finish translation block when an uncoditional branch is encountered
|
||||
done = true;
|
||||
continue;
|
||||
}
|
||||
|
||||
/* pre-decode operands, immediate values etc. */
|
||||
switch (p_instr->info.ops_fmt) {
|
||||
case InstrOps::opDA:
|
||||
c_instr->d1 = REG_D(opcode);
|
||||
c_instr->d2 = REG_A(opcode);
|
||||
break;
|
||||
case InstrOps::opDAB:
|
||||
c_instr->d1 = REG_D(opcode);
|
||||
c_instr->d2 = REG_A(opcode);
|
||||
c_instr->d3 = REG_B(opcode);
|
||||
break;
|
||||
case InstrOps::opDASimm:
|
||||
c_instr->d1 = REG_D(opcode);
|
||||
c_instr->d2 = REG_A(opcode);
|
||||
c_instr->simm = SIMM(opcode);
|
||||
break;
|
||||
case InstrOps::opSAUimm:
|
||||
c_instr->d1 = REG_S(opcode);
|
||||
c_instr->d2 = REG_A(opcode);
|
||||
c_instr->uimm = UIMM(opcode);
|
||||
break;
|
||||
case InstrOps::opSASh:
|
||||
c_instr->d1 = REG_S(opcode);
|
||||
c_instr->d2 = REG_A(opcode);
|
||||
c_instr->d3 = (opcode >> 11) & 0x1F; // shift
|
||||
c_instr->uimm = (1 << c_instr->d3) - 1; // mask
|
||||
break;
|
||||
case InstrOps::opRot:
|
||||
c_instr->d1 = REG_S(opcode);
|
||||
c_instr->d2 = REG_A(opcode);
|
||||
c_instr->d3 = (opcode >> 11) & 0x1F; // shift
|
||||
c_instr->d4 = opcode & 1; // Rc bit
|
||||
c_instr->uimm = rot_mask((opcode >> 6) & 31, (opcode >> 1) & 31); //mask
|
||||
break;
|
||||
case InstrOps::opSSpr:
|
||||
c_instr->d1 = REG_S(opcode);
|
||||
c_instr->uimm = (REG_B(opcode) << 5) | REG_A(opcode);
|
||||
break;
|
||||
case InstrOps::opBrRel:
|
||||
c_instr->bt = SIMM(opcode) >> 2;
|
||||
switch (BR_BO(opcode) & 0x1E) {
|
||||
case 12:
|
||||
case 14:
|
||||
c_instr->call_me = interp_tab[PPCInstr::bc].emu_fn;
|
||||
c_instr->uimm = 0x80000000UL >> BR_BI(opcode);
|
||||
break;
|
||||
case 16:
|
||||
c_instr->call_me = interp_tab[PPCInstr::bdnz].emu_fn;
|
||||
break;
|
||||
case 18:
|
||||
c_instr->call_me = interp_tab[PPCInstr::bdz].emu_fn;
|
||||
break;
|
||||
default:
|
||||
LOG_F(ERROR, "Unsupported opcode 0x%08X - Program exception!", opcode);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case InstrOps::opBrLink:
|
||||
switch (BR_BO(opcode) & 0x1E) {
|
||||
case 20: // blr
|
||||
c_instr->call_me = interp_tab[PPCInstr::bexit].emu_fn;
|
||||
c_instr->uimm = next_pc;
|
||||
done = true;
|
||||
continue;
|
||||
default:
|
||||
LOG_F(ERROR, "Unsupported opcode 0x%08X - Program exception!", opcode);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
LOG_F(ERROR, "Unknown opcode format %d!", p_instr->info.ops_fmt);
|
||||
return false;
|
||||
}
|
||||
|
||||
c_instr++;
|
||||
|
||||
next_pc += 4;
|
||||
pc_real += 4;
|
||||
ppc_set_cur_instruction(pc_real);
|
||||
} // while
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void NuInterpExec(uint32_t start_addr) {
|
||||
interp_tpc = &code_block[0];
|
||||
|
||||
if (!PreDecode(start_addr, interp_tpc)) {
|
||||
return;
|
||||
}
|
||||
|
||||
interp_running = true;
|
||||
|
||||
while(interp_running) {
|
||||
interp_tpc->call_me(interp_tpc);
|
||||
}
|
||||
}
|
||||
2
cpu/ppc/nuinterpreter.h
Normal file
2
cpu/ppc/nuinterpreter.h
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
//void PreDecode(uint32_t next_pc);
|
||||
void NuInterpExec(uint32_t start_addr);
|
||||
297
cpu/ppc/ppcdefs.h
Normal file
297
cpu/ppc/ppcdefs.h
Normal file
|
|
@ -0,0 +1,297 @@
|
|||
#ifndef PPC_DEFS_H
|
||||
#define PPC_DEFS_H
|
||||
|
||||
/* Enumerate all supported PowerPC instructions. */
|
||||
enum PPCInstr : int {
|
||||
illegal = 0,
|
||||
addi,
|
||||
adde,
|
||||
addze,
|
||||
andidot,
|
||||
lwz,
|
||||
lwzu,
|
||||
lbz,
|
||||
lhz,
|
||||
rlwinmx,
|
||||
srawidot,
|
||||
bc,
|
||||
bdnz,
|
||||
bdz,
|
||||
bclr,
|
||||
mtspr,
|
||||
bexit, // arificial block exit opcode
|
||||
|
||||
twi,
|
||||
mulli,
|
||||
subfic,
|
||||
cmpli,
|
||||
cmpi,
|
||||
addic,
|
||||
addicdot,
|
||||
addis,
|
||||
sc,
|
||||
rlwimix,
|
||||
rlwnmx,
|
||||
ori,
|
||||
oris,
|
||||
xori,
|
||||
xoris,
|
||||
andisdot,
|
||||
lbzu,
|
||||
stw,
|
||||
stwu,
|
||||
stb,
|
||||
stbu,
|
||||
lhzu,
|
||||
lha,
|
||||
lhau,
|
||||
sth,
|
||||
sthu,
|
||||
lmw,
|
||||
stmw,
|
||||
lfs,
|
||||
lfsu,
|
||||
lfd,
|
||||
lfdu,
|
||||
stfs,
|
||||
stfsu,
|
||||
stfd,
|
||||
stfdu,
|
||||
bcl,
|
||||
bca,
|
||||
bcla,
|
||||
b,
|
||||
bl,
|
||||
ba,
|
||||
bla,
|
||||
bclrl,
|
||||
crnor,
|
||||
rfi,
|
||||
crandc,
|
||||
isync,
|
||||
crxor,
|
||||
crnand,
|
||||
crand,
|
||||
creqv,
|
||||
crorc,
|
||||
cror,
|
||||
bcctr,
|
||||
bcctrl,
|
||||
cmp,
|
||||
tw,
|
||||
subfc,
|
||||
subfcdot,
|
||||
addc,
|
||||
addcdot,
|
||||
mulhwu,
|
||||
mulhwudot,
|
||||
mfcr,
|
||||
lwarx,
|
||||
lwzx,
|
||||
slw,
|
||||
slwdot,
|
||||
cntlzw,
|
||||
cntlzwdot,
|
||||
ppc_and,
|
||||
anddot,
|
||||
cmpl,
|
||||
subf,
|
||||
subfdot,
|
||||
dcbst,
|
||||
lwzux,
|
||||
andc,
|
||||
andcdot,
|
||||
mulhw,
|
||||
mulhwdot,
|
||||
mfmsr,
|
||||
dcbf,
|
||||
lbzx,
|
||||
neg,
|
||||
negdot,
|
||||
mul,
|
||||
muldot,
|
||||
lbzux,
|
||||
nor,
|
||||
nordot,
|
||||
subfe,
|
||||
subfedot,
|
||||
addedot,
|
||||
mtcrf,
|
||||
mtmsr,
|
||||
stwcx,
|
||||
stwx,
|
||||
stwux,
|
||||
subfze,
|
||||
subfzedot,
|
||||
addzedot,
|
||||
mtsr,
|
||||
stbx,
|
||||
subfme,
|
||||
subfmedot,
|
||||
addme,
|
||||
addmedot,
|
||||
mullw,
|
||||
mullwdot,
|
||||
mtsrin,
|
||||
dcbtst,
|
||||
stbux,
|
||||
add,
|
||||
adddot,
|
||||
lscbx,
|
||||
lscbxdot,
|
||||
dcbt,
|
||||
lhzx,
|
||||
eqv,
|
||||
eqvdot,
|
||||
tlbie,
|
||||
lhzux,
|
||||
ppc_xor,
|
||||
xordot,
|
||||
div,
|
||||
divdot,
|
||||
mfspr,
|
||||
lhax,
|
||||
abs,
|
||||
absdot,
|
||||
divs,
|
||||
divsdot,
|
||||
tlbia,
|
||||
mftb,
|
||||
lhaux,
|
||||
sthx,
|
||||
orc,
|
||||
orcdot,
|
||||
sthux,
|
||||
ppc_or,
|
||||
ordot,
|
||||
divwu,
|
||||
divwudot,
|
||||
dcbi,
|
||||
nand,
|
||||
nanddot,
|
||||
divw,
|
||||
divwdot,
|
||||
mcrxr,
|
||||
subfco,
|
||||
subfcodot,
|
||||
addco,
|
||||
addcodot,
|
||||
lswx,
|
||||
lwbrx,
|
||||
lfsx,
|
||||
srw,
|
||||
srwdot,
|
||||
subfo,
|
||||
subfodot,
|
||||
tlbsync,
|
||||
lfsux,
|
||||
mfsr,
|
||||
lswi,
|
||||
sync,
|
||||
lfdx,
|
||||
nego,
|
||||
negodot,
|
||||
mulo,
|
||||
mulodot,
|
||||
lfdux,
|
||||
subfeo,
|
||||
subfeodot,
|
||||
addeo,
|
||||
addeodot,
|
||||
mfsrin,
|
||||
stswx,
|
||||
stwbrx,
|
||||
stfsx,
|
||||
stfsux,
|
||||
subfzeo,
|
||||
subfzeodot,
|
||||
addzeo,
|
||||
addzeodot,
|
||||
stswi,
|
||||
stfdx,
|
||||
subfmeo,
|
||||
subfmeodot,
|
||||
addmeo,
|
||||
addmeodot,
|
||||
mullwo,
|
||||
mullwodot,
|
||||
stfdux,
|
||||
addo,
|
||||
addodot,
|
||||
lhbrx,
|
||||
sraw,
|
||||
srawdot,
|
||||
srawi,
|
||||
eieio,
|
||||
sthbrx,
|
||||
extsh,
|
||||
extshdot,
|
||||
extsb,
|
||||
extsbdot,
|
||||
divwuo,
|
||||
divwuodot,
|
||||
tlbld,
|
||||
icbi,
|
||||
stfiwx,
|
||||
divwo,
|
||||
divwodot,
|
||||
tlbli,
|
||||
dcbz,
|
||||
|
||||
// POWER-specific
|
||||
dozi,
|
||||
rlmi,
|
||||
maskg,
|
||||
maskgdot,
|
||||
slq,
|
||||
slqdot,
|
||||
sle,
|
||||
sledot,
|
||||
sliq,
|
||||
sllq,
|
||||
sllqdot,
|
||||
sleq,
|
||||
sleqdot,
|
||||
slliq,
|
||||
slliqdot,
|
||||
doz,
|
||||
dozdot,
|
||||
nabs,
|
||||
nabsdot,
|
||||
clcs,
|
||||
clcsdot,
|
||||
rrib,
|
||||
rribdot,
|
||||
maskir,
|
||||
maskirdot,
|
||||
srq,
|
||||
srqdot,
|
||||
sre,
|
||||
sredot,
|
||||
sriq,
|
||||
sriqdot,
|
||||
srlq,
|
||||
srlqdot,
|
||||
sreq,
|
||||
sreqdot,
|
||||
srliq,
|
||||
srliqdot,
|
||||
dozo,
|
||||
dozodot,
|
||||
divo,
|
||||
divodot,
|
||||
abso,
|
||||
absodot,
|
||||
divso,
|
||||
divsodot,
|
||||
sraq,
|
||||
sraqdot,
|
||||
srea,
|
||||
sreadot,
|
||||
sraiq,
|
||||
sraiqdot,
|
||||
nabso,
|
||||
nabsodot,
|
||||
};
|
||||
|
||||
#endif /* PPC_DEFS_H */
|
||||
Loading…
Reference in New Issue
Block a user