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Continued clean-up, part 3
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@ -39,7 +39,7 @@ inline void power_setsoov(uint32_t a, uint32_t b, uint32_t d) {
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/** mask generator for rotate and shift instructions (§ 4.2.1.4 PowerpC PEM) */
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static inline uint32_t power_rot_mask(unsigned rot_mb, unsigned rot_me) {
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uint32_t m1 = 0xFFFFFFFFUL >> rot_mb;
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uint32_t m2 = (uint32_t)(0xFFFFFFFFUL << (31 - rot_me));
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uint32_t m2 = uint32_t(0xFFFFFFFFUL << (31 - rot_me));
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return ((rot_mb <= rot_me) ? m2 & m1 : m1 | m2);
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}
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@ -79,14 +79,14 @@ void dppc_interpreter::power_clcs() {
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void dppc_interpreter::power_div() {
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ppc_grab_regsdab();
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uint64_t dividend = ((uint64_t)ppc_result_a << 32) | ppc_state.spr[SPR::MQ];
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uint64_t dividend = (uint64_t(ppc_result_a << 32)) | ppc_state.spr[SPR::MQ];
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int32_t divisor = ppc_result_b;
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if ((ppc_result_a == 0x80000000UL && divisor == -1) || !divisor) {
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ppc_state.spr[SPR::MQ] = 0;
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ppc_result_d = 0x80000000UL; // -2^31 aka INT32_MIN
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} else {
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ppc_result_d = (uint32_t)(dividend / divisor);
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ppc_result_d = uint32_t(dividend / divisor);
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ppc_state.spr[SPR::MQ] = dividend % divisor;
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}
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@ -113,7 +113,7 @@ void dppc_interpreter::power_divs() {
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void dppc_interpreter::power_doz() {
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ppc_grab_regsdab();
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ppc_result_d = ((int32_t)ppc_result_a >= (int32_t)ppc_result_b) ? 0 :
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ppc_result_d = (int32_t(ppc_result_a) >= int32_t(ppc_result_b)) ? 0 :
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ppc_result_b - ppc_result_a;
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if (rc_flag)
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@ -136,7 +136,7 @@ void dppc_interpreter::power_dozi() {
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void dppc_interpreter::power_lscbx() {
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ppc_grab_regsdab();
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ppc_effective_address = (reg_a == 0) ? ppc_result_b : ppc_result_a + ppc_result_b;
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ppc_effective_address = reg_a ? (ppc_result_a + ppc_result_b) : ppc_result_b;
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//ppc_result_d = 0xFFFFFFFF;
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uint8_t return_value = 0;
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@ -161,8 +161,6 @@ SUPERVISOR MODEL
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536 - 543 are the Data BAT registers
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**/
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extern uint32_t opcode_value; // used for interpreting opcodes
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extern uint64_t timebase_counter;
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extern uint64_t tbr_wr_timestamp;
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extern uint64_t dec_wr_timestamp;
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