diff --git a/CREDITS.md b/CREDITS.md
index 8bc850c..6794c66 100644
--- a/CREDITS.md
+++ b/CREDITS.md
@@ -8,7 +8,11 @@
 - joevt
 - mihaip
 
-## Building
+## NT4/PPC fork
+
+- Wack0
+
+## DevOps
 
 - Waqar144
 - webspacecreations
@@ -16,6 +20,8 @@
 - sdkmap
 - dressupgeekout
 - kth5
+- dyharlan
+- roytam1
 
 ## Testing
 
diff --git a/zdocs/developers/dbdma.md b/zdocs/developers/dbdma.md
new file mode 100644
index 0000000..3dcb600
--- /dev/null
+++ b/zdocs/developers/dbdma.md
@@ -0,0 +1,50 @@
+The Description-Based Direct Memory Access (DBDMA) relies on memory-based descriptions, minimizing CPU interrupts.
+
+| Channel           | Number |
+|:-----------------:|:------:|
+| SCSI0             | 0x0    |
+| FLOPPY            | 0x1    |
+| ETHERNET TRANSMIT | 0x2    |
+| ETHERNET RECIEVE  | 0x3    |
+| SCC TRANSMIT A    | 0x4    |
+| SCC RECIEVE A     | 0x5    |
+| SCC TRANSMIT B    | 0x6    |
+| SCC RECIEVE B     | 0x7    |
+| AUDIO OUT         | 0x8    |
+| AUDIO IN          | 0x9    |
+| SCSI1             | 0xA    |
+
+| Register          | Offset |
+|:-----------------:|:------:|
+| ChannelControl    | 0x00   |
+| ChannelStatus     | 0x04   |
+| CommandPtrLo      | 0x0C   |
+| InterruptSelect   | 0x10   |
+| BranchSelect      | 0x14   |
+| WaitSelect        | 0x18   |
+
+| Command           | Value  |
+|:-----------------:|:------:|
+| OUTPUT_MORE       | 0x0    |
+| OUTPUT_LAST       | 0x1    |
+| INPUT_MORE        | 0x2    |
+| INPUT_LAST        | 0x3    |
+| STORE_QUAD        | 0x4    |
+| LOAD_QUAD         | 0x5    |
+| NOP               | 0x6    |
+| STOP              | 0x7    |
+
+| Key Name          | Value  |
+|:-----------------:|:------:|
+| KEY_STREAM0       | 0x0    |
+| KEY_STREAM1       | 0x1    |
+| KEY_STREAM2       | 0x2    |
+| KEY_STREAM3       | 0x3    |
+| KEY_REGS          | 0x5    |
+| KEY_SYSTEM        | 0x6    |
+| KEY_DEVICE        | 0x7    |
+
+# References
+
+* https://stuff.mit.edu/afs/sipb/contrib/doc/specs/protocol/chrp/chrp_io.pdf
+* https://stuff.mit.edu/afs/sipb/contrib/doc/specs/protocol/chrp/chrp_hrpa.pdf
\ No newline at end of file
diff --git a/zdocs/developers/heathrow.md b/zdocs/developers/heathrow.md
index cbc85f5..52d0bd4 100644
--- a/zdocs/developers/heathrow.md
+++ b/zdocs/developers/heathrow.md
@@ -1,6 +1,6 @@
 # Heathrow ASIC
 
-The Heathrow ASIC is an intergrated I/O controller designed for use in Power
+The Heathrow ASIC is an integrated I/O controller designed for use in Power
 Macintosh G3 computers.
 
 Its predecessors are Grand Central and O'Hare ASICs used in other Power Macintosh
@@ -17,7 +17,7 @@ I/O hardware to the PCI-based Power Macintosh. That legacy hardware has
 existed long before Power Macintosh was introduced. It includes:
 - versatile interface adapter (VIA)
 - Sander-Woz integrated machine (SWIM) that is a floppy disk controller
-- CUDA MCU that controls ADB, parameter RAM, realtime clock and power management
+- CUDA MCU that controls ADB, parameter RAM, real time clock and power management
 - serial communication controller (SCC)
 - Macintosh Enhanced SCSI Hardware (MESH)
 
@@ -90,7 +90,7 @@ Macintosh firmware configures the Heathrow ASIC to live at address `0xF3000000`.
 | 0x30   | UnknownReg30      | Not much is known about this register          |
 | 0x34   | HeathrowIDs       | bits for identifying media bay features?       |
 | 0x38   | FeatureControl    | bits for controlling Heathrow operation        |
-| 0x3C   | AuxControl        | auxilary control bits                          |
+| 0x3C   | AuxControl        | auxiliary control bits                          |
 
 ### Device DMA spaces
 
diff --git a/zdocs/developers/misc.md b/zdocs/developers/misc.md
index 290d6ba..be7897f 100644
--- a/zdocs/developers/misc.md
+++ b/zdocs/developers/misc.md
@@ -10,24 +10,6 @@ Within Apple, the project to overhaul Mac OS ROM code from separate portable, lo
 
 For serial, it replicates the functionality of a Zilog ESCC. There are two different ports - one located at (MacIOBase) + 0x13000 for the printer, and the other at (MacIOBase) + 0x13020 for the modem.
 
-# DBDMA
-
-The Description-Based Direct Memory Access relies on memory-based descriptions, minimizing CPU interrupts.
-
-| Channel           | Number |
-|:-----------------:|:------:|
-| SCSI0             | 0x0    |
-| FLOPPY            | 0x1    |
-| ETHERNET TRANSMIT | 0x2    |
-| ETHERNET RECIEVE  | 0x3    |
-| SCC TRANSMIT A    | 0x4    |
-| SCC RECIEVE A     | 0x5    |
-| SCC TRANSMIT B    | 0x6    |
-| SCC RECIEVE B     | 0x7    |
-| AUDIO OUT         | 0x8    |
-| AUDIO IN          | 0x9    |
-| SCSI1             | 0xA    |
-
 # NCR 53C94
 
 The NCR 53C94 is the SCSI controller.
diff --git a/zdocs/developers/powerpc.md b/zdocs/developers/powerpc.md
index 0c1341b..11513f4 100644
--- a/zdocs/developers/powerpc.md
+++ b/zdocs/developers/powerpc.md
@@ -80,4 +80,8 @@ Up to 128 instruction entries and 128 data entries can be stored at a time.
 
 * The 603 relies on the instructions tlbld and tlbli to assist in TLB reloading.
 
-* To accomodate for early programs compiled on PowerPC 601 Macs, the classic Mac OS has to emulate the POWER instructions that were removed from later processors.
\ No newline at end of file
+* To accommodate for early programs compiled on PowerPC 601 Macs, the classic Mac OS has to emulate the POWER instructions that were removed from later processors.
+
+# References
+
+http://www.ibmfiles.com/ibmfiles/powerpc/itso_powerpc_inside_view.pdf