mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-12-24 12:30:05 +00:00
Floating point overhaul, part 1
Cleaned up formatting and reworked the INF/NAN checks
This commit is contained in:
dingusdev
parent
d5960ca70b
commit
e344b089b3
@ -200,6 +200,70 @@ enum class BB_end_kind {
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BB_RFI /* the rfi instruction is encountered */
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};
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enum class CR_select {
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CR0_field = (0xF << 28),
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};
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enum class CRx_bit {
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CR_SO = 0,
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CR_EQ,
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CR_GT,
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CR_LT
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};
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enum class CR1_bit {
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CR1_OX = 24,
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CR1_VX,
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CR1_FEX,
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CR1_FX,
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};
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enum class FPSCR_bit {
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FPSCR_RN = 0x3,
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FPSCR_NI = 0x4,
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FPSCR_XE = 0x8,
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FPSCR_ZE = 0x10,
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FPSCR_UE = 0x20,
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FPSCR_OE = 0x40,
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FPSCR_VE = 0x80,
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FPSCR_VXCVI = 0x100,
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FPSCR_VXSQRT = 0x200,
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FPSCR_VXSOFT = 0x400,
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FPSCR_FPRF = 0x1F000,
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FPSCR_FPCC_FUNAN = 0x10000,
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FPSCR_FPCC_ZERO = 0x8000,
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FPSCR_FPCC_POS = 0x4000,
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FPSCR_FPCC_NEG = 0x2000,
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FPSCR_FPCC_FPRCD = 0x1000,
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FPSCR_FI = (1 << 17),
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FPSCR_FR = (1 << 18),
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FPSCR_VXVC = (1 << 19),
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FPSCR_VXIMZ = (1 << 20),
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FPSCR_VXZDZ = (1 << 21),
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FPSCR_VXIDI = (1 << 22),
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FPSCR_VXISI = (1 << 23),
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FPSCR_VXSNAN = (1 << 24),
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FPSCR_XX = (1 << 25),
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FPSCR_ZX = (1 << 26),
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FPSCR_UX = (1 << 27),
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FPSCR_OX = (1 << 28),
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FPSCR_VX = (1 << 29),
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FPSCR_FEX = (1 << 30),
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FPSCR_FX = (1 << 31)
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};
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//for inf and nan checks
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enum FPOP : int {
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DIV = 0x12,
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SUB = 0x14,
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ADD = 0x15,
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MUL = 0x19,
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FMSUB = 0x1C,
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FMADD = 0x1D,
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FNMSUB = 0x1E,
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FNMADD = 0x1F,
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};
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/** PowerPC exception types. */
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enum class Except_Type {
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EXC_SYSTEM_RESET = 1,
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@ -271,7 +335,6 @@ void ppc_opcode63();
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void initialize_ppc_opcode_tables();
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extern bool ppc_confirm_inf_nan(uint64_t input_a, uint64_t input_b, bool is_single, uint32_t op);
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extern double fp_return_double(uint32_t reg);
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extern uint64_t fp_return_uint64(uint32_t reg);
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@ -253,8 +253,7 @@ void ppc_opcode31() {
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oe_flag = ppc_cur_instruction & 0x400;
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#ifdef EXHAUSTIVE_DEBUG
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uint32_t regrab = (uint32_t)subop_grab;
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LOG_F(INFO, "Executing Opcode 63 table subopcode entry \n", regrab);
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LOG_F(INFO, "Executing Opcode 31 table subopcode entry %n \n", (uint32_t)subop_grab);
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#endif // EXHAUSTIVE_DEBUG
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SubOpcode31Grabber[subop_grab]();
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@ -264,8 +263,7 @@ void ppc_opcode59() {
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uint16_t subop_grab = (ppc_cur_instruction >> 1) & 0x1F;
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rc_flag = ppc_cur_instruction & 1;
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#ifdef EXHAUSTIVE_DEBUG
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uint32_t regrab = (uint32_t)subop_grab;
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LOG_F(INFO, "Executing Opcode 59 table subopcode entry \n", regrab);
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LOG_F(INFO, "Executing Opcode 59 table subopcode entry %n \n", (uint32_t)subop_grab);
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#endif // EXHAUSTIVE_DEBUG
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SubOpcode59Grabber[subop_grab]();
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}
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@ -274,8 +272,7 @@ void ppc_opcode63() {
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uint16_t subop_grab = (ppc_cur_instruction >> 1) & 0x3FF;
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rc_flag = ppc_cur_instruction & 1;
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#ifdef EXHAUSTIVE_DEBUG
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uint32_t regrab = (uint32_t)subop_grab;
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LOG_F(INFO, "Executing Opcode 63 table subopcode entry \n", regrab);
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LOG_F(INFO, "Executing Opcode 63 table subopcode entry %n \n", (uint32_t)subop_grab);
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#endif // EXHAUSTIVE_DEBUG
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SubOpcode63Grabber[subop_grab]();
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}
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@ -25,6 +25,7 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
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#include "ppcmmu.h"
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#include <array>
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#include <cfenv>
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#include <cfloat>
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#include <cinttypes>
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#include <cmath>
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#include <iostream>
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@ -179,141 +180,115 @@ int64_t round_to_neg_inf(double f) {
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return static_cast<int32_t>(floor(f));
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}
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void ppc_toggle_fpscr_fex() {
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bool fex_result = ((ppc_state.fpscr & 0x20000000) & (ppc_state.fpscr & 0x80));
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fex_result |= ((ppc_state.fpscr & 0x10000000) & (ppc_state.fpscr & 0x40));
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fex_result |= ((ppc_state.fpscr & 0x8000000) & (ppc_state.fpscr & 0x20));
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fex_result |= ((ppc_state.fpscr & 0x4000000) & (ppc_state.fpscr & 0x10));
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fex_result |= ((ppc_state.fpscr & 0x2000000) & (ppc_state.fpscr & 0x8));
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ppc_state.fpscr |= (fex_result << 30);
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void update_fpscr_fex() {
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int fex_result = !!((ppc_state.fpscr & (ppc_state.fpscr << 22)) & 0x3E000000);
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ppc_state.fpscr = (ppc_state.fpscr & ~0x40000000) | (fex_result << 30);
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}
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bool ppc_confirm_inf_nan(int chosen_reg_1, int chosen_reg_2, bool is_single, uint32_t op) {
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uint64_t input_a = ppc_state.fpr[chosen_reg_1].int64_r;
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uint64_t input_b = ppc_state.fpr[chosen_reg_2].int64_r;
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template <typename T>
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constexpr auto ppc_confirm_inf_nan(int chosen_reg_1, int chosen_reg_2, int chosen_reg_3, uint32_t op) {
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T input_a = T(ppc_state.fpr[chosen_reg_1].int64_r);
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T input_b = T(ppc_state.fpr[chosen_reg_2].int64_r);
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T input_c = T(ppc_state.fpr[chosen_reg_3].int64_r);
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if (is_single) {
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uint32_t exp_a = (input_a >> 23) & 0xff;
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uint32_t exp_b = (input_b >> 23) & 0xff;
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ppc_state.fpscr &= 0x7fbfffff;
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ppc_state.fpscr &= 0x7fbfffff;
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bool inf_or_nan = false;
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switch (op) {
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case 36:
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if ((exp_a == 0xff) && (exp_b == 0xff)) {
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ppc_state.fpscr |= 0x80400000;
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ppc_toggle_fpscr_fex();
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return true;
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} else if ((input_a == 0) && (input_b == 0)) {
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ppc_state.fpscr |= 0x80200000;
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ppc_toggle_fpscr_fex();
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return true;
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switch (op) {
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case FPOP::DIV:
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if (isnan(input_a) && isnan(input_b)) {
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ppc_state.fpscr |= ((uint32_t)FPSCR_bit::FPSCR_FX | (uint32_t)FPSCR_bit::FPSCR_VXIDI);
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inf_or_nan = true;
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} else if ((input_a == FP_ZERO) && (input_b == FP_ZERO)) {
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ppc_state.fpscr |= ((uint32_t)FPSCR_bit::FPSCR_FX | (uint32_t)FPSCR_bit::FPSCR_VXZDZ);
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inf_or_nan = true;
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}
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update_fpscr_fex();
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return inf_or_nan;
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break;
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case 40:
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if ((exp_a == 0xff) && (exp_b == 0xff)) {
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ppc_state.fpscr |= 0x80800000;
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ppc_toggle_fpscr_fex();
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return true;
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case FPOP::SUB:
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if (isnan(input_a) && isnan(input_b)) {
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ppc_state.fpscr |= ((uint32_t)FPSCR_bit::FPSCR_FX | (uint32_t)FPSCR_bit::FPSCR_VXISI);
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inf_or_nan = true;
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}
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update_fpscr_fex();
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return inf_or_nan;
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break;
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case 50:
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if (((exp_a == 0xff) & (input_b == 0)) | ((exp_b == 0xff) & (input_a == 0))) {
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case FPOP::ADD:
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if ((isnan(input_a) & (input_b == FP_ZERO)) | (isnan(input_b) & (input_a == FP_ZERO))) {
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ppc_state.fpscr |= 0x80100000;
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ppc_toggle_fpscr_fex();
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return true;
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inf_or_nan = true;
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}
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update_fpscr_fex();
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return inf_or_nan;
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break;
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case 56:
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case 58:
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if ((exp_a == 0xff) && (exp_b == 0xff)) {
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ppc_state.fpscr |= 0x80800000;
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ppc_toggle_fpscr_fex();
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return true;
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case FPOP::MUL:
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if (((input_a == FP_ZERO) && (input_c == FP_INFINITE)) ||
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((input_c == FP_ZERO) && (input_a == FP_INFINITE))) {
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ppc_state.fpscr |=
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((uint32_t)FPSCR_bit::FPSCR_FX | (uint32_t)FPSCR_bit::FPSCR_VXSNAN |
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(uint32_t)FPSCR_bit::FPSCR_VXIMZ);
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inf_or_nan = true;
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}
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update_fpscr_fex();
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return inf_or_nan;
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break;
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case FPOP::FMSUB:
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case FPOP::FNMSUB:
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if (isnan(input_a) || isnan(input_b) || isnan(input_c)) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN;
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inf_or_nan = true;
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if (((input_a == FP_ZERO) && (input_c == FP_INFINITE)) ||
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((input_c == FP_ZERO) && (input_a == FP_INFINITE))) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXIMZ;
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}
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}
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update_fpscr_fex();
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return inf_or_nan;
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break;
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case FPOP::FMADD:
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case FPOP::FNMADD:
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if (isnan(input_a) || isnan(input_b) || isnan(input_c)) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN;
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inf_or_nan = true;
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}
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update_fpscr_fex();
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return inf_or_nan;
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break;
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default:
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return false;
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}
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} else {
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uint32_t exp_a = (input_a >> 52) & 0x7ff;
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uint32_t exp_b = (input_b >> 52) & 0x7ff;
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ppc_state.fpscr &= 0x7fbfffff;
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switch (op) {
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case 36:
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if ((exp_a == 0x7ff) && (exp_b == 0x7ff)) {
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ppc_state.fpscr |= 0x80400000;
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ppc_toggle_fpscr_fex();
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return true;
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} else if ((input_a == 0) && (input_b == 0)) {
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ppc_state.fpscr |= 0x80200000;
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ppc_toggle_fpscr_fex();
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return true;
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}
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break;
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case 40:
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if ((exp_a == 0x7ff) && (exp_b == 0x7ff)) {
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ppc_state.fpscr |= 0x80800000;
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ppc_toggle_fpscr_fex();
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return true;
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}
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break;
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case 50:
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if (((exp_a == 0x7ff) & (input_b == 0)) | ((exp_b == 0x7ff) & (input_a == 0))) {
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ppc_state.fpscr |= 0x80100000;
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ppc_toggle_fpscr_fex();
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return true;
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}
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break;
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case 56:
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case 58:
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if ((exp_a == 0xff) && (exp_b == 0xff)) {
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ppc_state.fpscr |= 0x80800000;
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ppc_toggle_fpscr_fex();
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return true;
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}
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break;
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default:
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return false;
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}
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}
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return false;
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}
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void fpresult_update(uint64_t set_result, bool confirm_arc) {
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void fpresult_update(double set_result, bool confirm_arc) {
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bool confirm_ov = (bool)std::fetestexcept(FE_OVERFLOW);
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if (confirm_ov) {
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ppc_state.fpscr |= 0x80001000;
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ppc_state.fpscr |= ((uint32_t)FPSCR_bit::FPSCR_FX | ((uint32_t)FPSCR_bit::FPSCR_FPRF & (uint32_t)FPSCR_bit::FPSCR_FPCC_FUNAN));
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}
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if (confirm_arc) {
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ppc_state.fpscr |= 0x80010000;
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ppc_state.fpscr |= ((uint32_t)FPSCR_bit::FPSCR_FX | ((uint32_t)FPSCR_bit::FPSCR_FPRF & (uint32_t)FPSCR_bit::FPSCR_FPCC_FUNAN));
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ppc_state.fpscr &= 0xFFFF0FFF;
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if (set_result == 0) {
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ppc_state.fpscr |= 0x2000;
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if (set_result == 0.0) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_FPCC_NEG;
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} else {
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if (set_result < 0) {
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ppc_state.fpscr |= 0x8000;
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} else if (set_result > 0) {
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ppc_state.fpscr |= 0x4000;
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if (set_result < 0.0) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_FPCC_ZERO;
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} else if (set_result > 0.0) {
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_FPCC_POS;
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} else {
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ppc_state.fpscr |= 0x1000;
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ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_FPCC_FPRCD;
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}
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}
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}
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}
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void ppc_frsqrte_result() {
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if (ppc_result64_d & 0x007FF000000000000UL) {
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}
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}
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void ppc_changecrf1() {
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ppc_state.cr &= 0xF0FFFFFF;
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ppc_state.cr |= (ppc_state.fpscr & 0xF0000000) >> 4;
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@ -323,7 +298,7 @@ void ppc_changecrf1() {
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void dppc_interpreter::ppc_fadd() {
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ppc_grab_regsfpdab();
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if (!ppc_confirm_inf_nan(reg_a, reg_b, false, 58)) {
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if (!ppc_confirm_inf_nan<double>(reg_a, reg_b, 0, FPOP::ADD)) {
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ppc_dblresult64_d = val_reg_a + val_reg_b;
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ppc_store_dfpresult_flt(reg_d);
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}
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@ -335,7 +310,7 @@ void dppc_interpreter::ppc_fadd() {
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void dppc_interpreter::ppc_fsub() {
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ppc_grab_regsfpdab();
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if (!ppc_confirm_inf_nan(reg_a, reg_b, false, 56)) {
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if (!ppc_confirm_inf_nan<double>(reg_a, reg_b, 0, FPOP::SUB)) {
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ppc_dblresult64_d = val_reg_a - val_reg_b;
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ppc_store_dfpresult_flt(reg_d);
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}
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@ -347,7 +322,7 @@ void dppc_interpreter::ppc_fsub() {
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void dppc_interpreter::ppc_fdiv() {
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ppc_grab_regsfpdab();
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if (!ppc_confirm_inf_nan(reg_a, reg_b, false, 36)) {
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if (!ppc_confirm_inf_nan<double>(reg_a, reg_b, 0, FPOP::DIV)) {
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ppc_dblresult64_d = val_reg_a / val_reg_b;
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ppc_store_dfpresult_flt(reg_d);
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}
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@ -359,7 +334,7 @@ void dppc_interpreter::ppc_fdiv() {
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void dppc_interpreter::ppc_fmul() {
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ppc_grab_regsfpdac();
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if (!ppc_confirm_inf_nan(reg_a, reg_c, false, 50)) {
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if (!ppc_confirm_inf_nan<double>(reg_a, reg_c, 0, FPOP::MUL)) {
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ppc_dblresult64_d = val_reg_a * val_reg_c;
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ppc_store_dfpresult_flt(reg_d);
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}
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@ -371,14 +346,11 @@ void dppc_interpreter::ppc_fmul() {
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void dppc_interpreter::ppc_fmadd() {
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ppc_grab_regsfpdabc();
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if (!ppc_confirm_inf_nan(reg_a, reg_c, false, 50)) {
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ppc_dblresult64_d = (val_reg_a * val_reg_c);
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if (!ppc_confirm_inf_nan(reg_a, reg_b, false, 58)) {
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ppc_dblresult64_d += val_reg_b;
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}
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if (!ppc_confirm_inf_nan<double>(reg_a, reg_b, reg_c, FPOP::FMADD)) {
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ppc_dblresult64_d = std::fma(val_reg_a, val_reg_c, val_reg_b);
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ppc_store_dfpresult_flt(reg_d);
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||||
}
|
||||
|
||||
ppc_store_dfpresult_flt(reg_d);
|
||||
|
||||
if (rc_flag)
|
||||
ppc_changecrf1();
|
||||
@ -387,14 +359,12 @@ void dppc_interpreter::ppc_fmadd() {
|
||||
void dppc_interpreter::ppc_fmsub() {
|
||||
ppc_grab_regsfpdabc();
|
||||
|
||||
if (!ppc_confirm_inf_nan(reg_a, reg_c, false, 50)) {
|
||||
if (!ppc_confirm_inf_nan<double>(reg_a, reg_b, reg_c, FPOP::FMSUB)) {
|
||||
ppc_dblresult64_d = (val_reg_a * val_reg_c);
|
||||
if (!ppc_confirm_inf_nan(reg_d, reg_b, false, 56)) {
|
||||
ppc_dblresult64_d -= val_reg_b;
|
||||
}
|
||||
ppc_dblresult64_d -= val_reg_b;
|
||||
ppc_store_dfpresult_flt(reg_d);
|
||||
}
|
||||
|
||||
ppc_store_dfpresult_flt(reg_d);
|
||||
|
||||
if (rc_flag)
|
||||
ppc_changecrf1();
|
||||
@ -403,16 +373,13 @@ void dppc_interpreter::ppc_fmsub() {
|
||||
void dppc_interpreter::ppc_fnmadd() {
|
||||
ppc_grab_regsfpdabc();
|
||||
|
||||
if (!ppc_confirm_inf_nan(reg_a, reg_c, false, 50)) {
|
||||
if (!ppc_confirm_inf_nan<double>(reg_a, reg_b, reg_c, FPOP::FNMADD)) {
|
||||
ppc_dblresult64_d = (val_reg_a * val_reg_c);
|
||||
if (!ppc_confirm_inf_nan(reg_a, reg_b, false, 58)) {
|
||||
ppc_dblresult64_d += val_reg_b;
|
||||
}
|
||||
ppc_dblresult64_d += val_reg_b;
|
||||
ppc_dblresult64_d = -ppc_dblresult64_d;
|
||||
ppc_store_dfpresult_flt(reg_d);
|
||||
}
|
||||
|
||||
ppc_dblresult64_d = -ppc_dblresult64_d;
|
||||
ppc_store_dfpresult_flt(reg_d);
|
||||
|
||||
if (rc_flag)
|
||||
ppc_changecrf1();
|
||||
}
|
||||
@ -420,15 +387,12 @@ void dppc_interpreter::ppc_fnmadd() {
|
||||
void dppc_interpreter::ppc_fnmsub() {
|
||||
ppc_grab_regsfpdabc();
|
||||
|
||||
if (!ppc_confirm_inf_nan(reg_a, reg_c, false, 50)) {
|
||||
if (!ppc_confirm_inf_nan<double>(reg_a, reg_b, reg_c, FPOP::FNMSUB)) {
|
||||
ppc_dblresult64_d = (val_reg_a * val_reg_c);
|
||||
if (!ppc_confirm_inf_nan(reg_d, reg_b, false, 56)) {
|
||||
ppc_dblresult64_d -= val_reg_b;
|
||||
}
|
||||
ppc_dblresult64_d -= val_reg_b;
|
||||
ppc_store_dfpresult_flt(reg_d);
|
||||
}
|
||||
ppc_dblresult64_d = -ppc_dblresult64_d;
|
||||
|
||||
ppc_store_dfpresult_flt(reg_d);
|
||||
|
||||
if (rc_flag)
|
||||
ppc_changecrf1();
|
||||
@ -437,7 +401,7 @@ void dppc_interpreter::ppc_fnmsub() {
|
||||
void dppc_interpreter::ppc_fadds() {
|
||||
ppc_grab_regsfpdab();
|
||||
|
||||
if (!ppc_confirm_inf_nan(reg_a, reg_b, true, 58)) {
|
||||
if (!ppc_confirm_inf_nan<float>(reg_a, reg_b, 0, FPOP::ADD)) {
|
||||
float intermediate = (float)val_reg_a + (float)val_reg_b;
|
||||
ppc_dblresult64_d = static_cast<double>(intermediate);
|
||||
ppc_store_sfpresult_flt(reg_d);
|
||||
@ -450,7 +414,7 @@ void dppc_interpreter::ppc_fadds() {
|
||||
void dppc_interpreter::ppc_fsubs() {
|
||||
ppc_grab_regsfpdab();
|
||||
|
||||
if (!ppc_confirm_inf_nan(reg_a, reg_b, true, 56)) {
|
||||
if (!ppc_confirm_inf_nan<float>(reg_a, reg_b, 0, FPOP::SUB)) {
|
||||
float intermediate = (float)val_reg_a - (float)val_reg_b;
|
||||
ppc_dblresult64_d = static_cast<double>(intermediate);
|
||||
ppc_store_sfpresult_flt(reg_d);
|
||||
@ -463,7 +427,7 @@ void dppc_interpreter::ppc_fsubs() {
|
||||
void dppc_interpreter::ppc_fmuls() {
|
||||
ppc_grab_regsfpdac();
|
||||
|
||||
if (!ppc_confirm_inf_nan(reg_a, reg_c, true, 50)) {
|
||||
if (!ppc_confirm_inf_nan<float>(reg_a, 0, reg_c, FPOP::MUL)) {
|
||||
float intermediate = (float)val_reg_a * (float)val_reg_c;
|
||||
ppc_dblresult64_d = static_cast<double>(intermediate);
|
||||
ppc_store_sfpresult_flt(reg_d);
|
||||
@ -476,7 +440,7 @@ void dppc_interpreter::ppc_fmuls() {
|
||||
void dppc_interpreter::ppc_fdivs() {
|
||||
ppc_grab_regsfpdab();
|
||||
|
||||
if (!ppc_confirm_inf_nan(reg_a, reg_b, true, 36)) {
|
||||
if (!ppc_confirm_inf_nan<float>(reg_a, reg_b, 0, FPOP::DIV)) {
|
||||
float intermediate = (float)val_reg_a / (float)val_reg_b;
|
||||
ppc_dblresult64_d = static_cast<double>(intermediate);
|
||||
ppc_store_sfpresult_flt(reg_d);
|
||||
@ -491,14 +455,11 @@ void dppc_interpreter::ppc_fmadds() {
|
||||
|
||||
float intermediate;
|
||||
|
||||
if (!ppc_confirm_inf_nan(reg_a, reg_b, true, 58)) {
|
||||
intermediate = (float)val_reg_a * (float)val_reg_c;
|
||||
if (!ppc_confirm_inf_nan(reg_a, reg_b, true, 58)) {
|
||||
intermediate += (float)val_reg_b;
|
||||
ppc_dblresult64_d = static_cast<double>(intermediate);
|
||||
if (!ppc_confirm_inf_nan<float>(reg_a, reg_b, reg_c, FPOP::FMADD)) {
|
||||
ppc_dblresult64_d = static_cast<double>(std::fma(
|
||||
(float)val_reg_a, (float)val_reg_c, (float)val_reg_b));
|
||||
|
||||
ppc_store_sfpresult_flt(reg_d);
|
||||
}
|
||||
ppc_store_sfpresult_flt(reg_d);
|
||||
}
|
||||
|
||||
if (rc_flag)
|
||||
@ -510,14 +471,12 @@ void dppc_interpreter::ppc_fmsubs() {
|
||||
|
||||
float intermediate;
|
||||
|
||||
if (!ppc_confirm_inf_nan(reg_a, reg_c, false, 50)) {
|
||||
if (!ppc_confirm_inf_nan<float>(reg_a, reg_b, reg_c, FPOP::FMSUB)) {
|
||||
intermediate = (float)val_reg_a * (float)val_reg_c;
|
||||
if (!ppc_confirm_inf_nan(reg_d, reg_b, false, 56)) {
|
||||
intermediate -= (float)val_reg_b;
|
||||
ppc_dblresult64_d = static_cast<double>(intermediate);
|
||||
intermediate -= (float)val_reg_b;
|
||||
ppc_dblresult64_d = static_cast<double>(intermediate);
|
||||
|
||||
ppc_store_sfpresult_flt(reg_d);
|
||||
}
|
||||
ppc_store_sfpresult_flt(reg_d);
|
||||
}
|
||||
|
||||
if (rc_flag)
|
||||
@ -529,16 +488,14 @@ void dppc_interpreter::ppc_fnmadds() {
|
||||
|
||||
float intermediate;
|
||||
|
||||
if (!ppc_confirm_inf_nan(reg_a, reg_b, true, 58)) {
|
||||
if (!ppc_confirm_inf_nan<float>(reg_a, reg_b, reg_c, FPOP::FNMADD)) {
|
||||
intermediate = (float)val_reg_a * (float)val_reg_c;
|
||||
if (!ppc_confirm_inf_nan(reg_a, reg_b, true, 58)) {
|
||||
intermediate += (float)val_reg_b;
|
||||
intermediate = -intermediate;
|
||||
intermediate += (float)val_reg_b;
|
||||
intermediate = -intermediate;
|
||||
|
||||
ppc_dblresult64_d = static_cast<double>(intermediate);
|
||||
ppc_dblresult64_d = static_cast<double>(intermediate);
|
||||
|
||||
ppc_store_sfpresult_flt(reg_d);
|
||||
}
|
||||
ppc_store_sfpresult_flt(reg_d);
|
||||
}
|
||||
|
||||
if (rc_flag)
|
||||
@ -550,16 +507,14 @@ void dppc_interpreter::ppc_fnmsubs() {
|
||||
|
||||
float intermediate;
|
||||
|
||||
if (!ppc_confirm_inf_nan(reg_a, reg_c, false, 50)) {
|
||||
if (!ppc_confirm_inf_nan<float>(reg_a, reg_b, reg_c, FPOP::FNMSUB)) {
|
||||
intermediate = (float)val_reg_a * (float)val_reg_c;
|
||||
if (!ppc_confirm_inf_nan(reg_d, reg_b, false, 56)) {
|
||||
intermediate -= (float)val_reg_b;
|
||||
intermediate = -intermediate;
|
||||
intermediate -= (float)val_reg_b;
|
||||
intermediate = -intermediate;
|
||||
|
||||
ppc_dblresult64_d = static_cast<double>(intermediate);
|
||||
ppc_dblresult64_d = static_cast<double>(intermediate);
|
||||
|
||||
ppc_store_sfpresult_flt(reg_d);
|
||||
}
|
||||
ppc_store_sfpresult_flt(reg_d);
|
||||
}
|
||||
|
||||
if (rc_flag)
|
||||
@ -687,12 +642,16 @@ void dppc_interpreter::ppc_fctiw() {
|
||||
switch (ppc_state.fpscr & 0x3) {
|
||||
case 0:
|
||||
ppc_result64_d = round_to_nearest(val_reg_b);
|
||||
break;
|
||||
case 1:
|
||||
ppc_result64_d = round_to_zero(val_reg_b);
|
||||
break;
|
||||
case 2:
|
||||
ppc_result64_d = round_to_pos_inf(val_reg_b);
|
||||
break;
|
||||
case 3:
|
||||
ppc_result64_d = round_to_neg_inf(val_reg_b);
|
||||
break;
|
||||
}
|
||||
|
||||
ppc_store_dfpresult_int(reg_d);
|
||||
@ -1027,25 +986,28 @@ void dppc_interpreter::ppc_fcmpo() {
|
||||
ppc_state.fpscr &= 0xFFFF0FFF;
|
||||
|
||||
if (std::isnan(db_test_a) || std::isnan(db_test_b)) {
|
||||
cmp_c |= 0x01;
|
||||
cmp_c |= (1 << (uint32_t)CRx_bit::CR_SO);
|
||||
} else if (db_test_a < db_test_b) {
|
||||
cmp_c |= 0x08;
|
||||
cmp_c |= (1 << (uint32_t)CRx_bit::CR_LT);
|
||||
} else if (db_test_a > db_test_b) {
|
||||
cmp_c |= 0x04;
|
||||
cmp_c |= (1 << (uint32_t)CRx_bit::CR_GT);
|
||||
} else {
|
||||
cmp_c |= 0x02;
|
||||
cmp_c |= (1 << (uint32_t)CRx_bit::CR_EQ);
|
||||
}
|
||||
|
||||
ppc_state.fpscr |= (cmp_c << 12);
|
||||
ppc_state.cr = ((ppc_state.cr & ~(0xf0000000 >> crf_d)) | ((cmp_c + xercon) >> crf_d));
|
||||
fpresult_update(db_test_a, true);
|
||||
|
||||
if ((db_test_a == snan) || (db_test_b == snan)) {
|
||||
ppc_state.fpscr |= 0x1000000;
|
||||
ppc_state.fpscr = (ppc_state.fpscr & ~((uint32_t)FPSCR_bit::FPSCR_FPRF)) | (cmp_c << 12);
|
||||
ppc_state.cr =
|
||||
((ppc_state.cr & ~((uint32_t)CR_select::CR0_field >> crf_d)) | ((cmp_c + xercon) >> crf_d));
|
||||
|
||||
if (std::isnan(db_test_a) || std::isnan(db_test_b)) {
|
||||
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN;
|
||||
if (ppc_state.fpscr & 0x80) {
|
||||
ppc_state.fpscr |= 0x80000;
|
||||
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXVC;
|
||||
}
|
||||
} else if ((db_test_a == qnan) || (db_test_b == qnan)) {
|
||||
ppc_state.fpscr |= 0x80000;
|
||||
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXVC;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1055,19 +1017,22 @@ void dppc_interpreter::ppc_fcmpu() {
|
||||
ppc_state.fpscr &= 0xFFFF0FFF;
|
||||
|
||||
if (std::isnan(db_test_a) || std::isnan(db_test_b)) {
|
||||
cmp_c |= 0x01;
|
||||
cmp_c |= (1 << (uint32_t)CRx_bit::CR_SO);
|
||||
} else if (db_test_a < db_test_b) {
|
||||
cmp_c |= 0x08;
|
||||
cmp_c |= (1 << (uint32_t)CRx_bit::CR_LT);
|
||||
} else if (db_test_a > db_test_b) {
|
||||
cmp_c |= 0x04;
|
||||
cmp_c |= (1 << (uint32_t)CRx_bit::CR_GT);
|
||||
} else {
|
||||
cmp_c |= 0x02;
|
||||
cmp_c |= (1 << (uint32_t)CRx_bit::CR_EQ);
|
||||
}
|
||||
|
||||
ppc_state.fpscr |= (cmp_c << 12);
|
||||
ppc_state.cr = ((ppc_state.cr & ~(0xf0000000 >> crf_d)) | ((cmp_c + xercon) >> crf_d));
|
||||
fpresult_update(db_test_a, true);
|
||||
|
||||
if ((db_test_a == snan) || (db_test_b == snan)) {
|
||||
ppc_state.fpscr |= 0x1000000;
|
||||
ppc_state.fpscr = (ppc_state.fpscr & ~((uint32_t)FPSCR_bit::FPSCR_FPRF)) | (cmp_c << 12);
|
||||
ppc_state.cr =
|
||||
((ppc_state.cr & ~((uint32_t)CR_select::CR0_field >> crf_d)) | ((cmp_c + xercon) >> crf_d));
|
||||
|
||||
if (std::isnan(db_test_a) || std::isnan(db_test_b)) {
|
||||
ppc_state.fpscr |= (uint32_t)FPSCR_bit::FPSCR_VXSNAN;
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user