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Rename data conversion helpers for PCI config.
Reword some descriptions for better understanding.
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36dee46e9b
commit
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@ -166,7 +166,7 @@ uint32_t BanditHost::read(uint32_t rgn_start, uint32_t offset, int size)
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details.flags = PCI_CONFIG_TYPE_0 | PCI_CONFIG_READ;
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details.flags = PCI_CONFIG_TYPE_0 | PCI_CONFIG_READ;
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result = this->dev_map[idsel]->pci_cfg_read(REG_NUM(), details);
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result = this->dev_map[idsel]->pci_cfg_read(REG_NUM(), details);
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return pci_cfg_rev_read(result, details);
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return pci_conv_rd_data(result, details);
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} else {
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} else {
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LOG_F(
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LOG_F(
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ERROR, "%s err: read attempt from non-existing PCI device ??:%02x.%x @%02x",
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ERROR, "%s err: read attempt from non-existing PCI device ??:%02x.%x @%02x",
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@ -225,7 +225,7 @@ void BanditHost::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int
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this->dev_map[idsel]->pci_cfg_write(REG_NUM(), BYTESWAP_32(value), details);
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this->dev_map[idsel]->pci_cfg_write(REG_NUM(), BYTESWAP_32(value), details);
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} else { // otherwise perform necessary data transformations -> slow path
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} else { // otherwise perform necessary data transformations -> slow path
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uint32_t old_val = this->dev_map[idsel]->pci_cfg_read(REG_NUM(), details);
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uint32_t old_val = this->dev_map[idsel]->pci_cfg_read(REG_NUM(), details);
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uint32_t new_val = pci_cfg_rev_write(old_val, value, details);
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uint32_t new_val = pci_conv_wr_data(old_val, value, details);
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this->dev_map[idsel]->pci_cfg_write(REG_NUM(), new_val, details);
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this->dev_map[idsel]->pci_cfg_write(REG_NUM(), new_val, details);
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}
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}
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} else {
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} else {
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@ -116,12 +116,12 @@ protected:
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// PCI configuration space state
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// PCI configuration space state
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uint16_t vendor_id;
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uint16_t vendor_id;
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uint16_t device_id;
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uint16_t device_id;
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uint32_t class_rev; // class code and revision id
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uint32_t class_rev; // class code and revision id
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uint16_t status = 0;
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uint16_t status = 0;
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uint16_t command = 0;
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uint16_t command = 0;
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uint8_t hdr_type = 0; // header type
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uint8_t hdr_type = 0; // header type
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uint8_t lat_timer = 0; // latency timer
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uint8_t lat_timer = 0; // latency timer
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uint8_t cache_ln_sz = 0; // cache line size
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uint8_t cache_ln_sz = 0; // cache line size
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uint16_t subsys_id = 0;
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uint16_t subsys_id = 0;
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uint16_t subsys_vndr = 0;
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uint16_t subsys_vndr = 0;
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uint8_t cap_ptr = 0;
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uint8_t cap_ptr = 0;
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@ -72,9 +72,14 @@ protected:
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std::vector<PCIDevice*> io_space_devs;
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std::vector<PCIDevice*> io_space_devs;
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};
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};
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/* value is dword from PCI config. MSB..LSB of value is stored in PCI config as 0:LSB..3:MSB.
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// Helpers for data conversion in the PCI Configuration space.
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result is part of value at byte offset from LSB with size bytes (with wrap around) and flipped as required for pci_cfg_read result. */
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inline uint32_t pci_cfg_rev_read(uint32_t value, AccessDetails &details) {
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/**
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Perform size dependent endian swapping for value that is dword from PCI config.
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Unaligned data is handled properly by wrapping around if needed.
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*/
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inline uint32_t pci_conv_rd_data(uint32_t value, AccessDetails &details) {
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switch (details.size << 2 | details.offset) {
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switch (details.size << 2 | details.offset) {
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// Bytes
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// Bytes
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case 0x04:
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case 0x04:
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@ -110,10 +115,13 @@ inline uint32_t pci_cfg_rev_read(uint32_t value, AccessDetails &details) {
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}
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}
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}
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}
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/* value is dword from PCI config. MSB..LSB of value (3.2.1.0) is stored in PCI config as 0:LSB..3:MSB.
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/**
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newvalue is flipped bytes (d0.d1.d2.d3, as passed to pci_cfg_write) to be merged into value.
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Perform size dependent endian swapping for v2, then merge v2 with v1 under
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result is part of value at byte offset from LSB with size bytes (with wrap around) modified by newvalue. */
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control of a mask generated according with the size parameter.
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inline uint32_t pci_cfg_rev_write(uint32_t v1, uint32_t v2, AccessDetails &details)
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Unaligned data is handled properly by wrapping around if needed.
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*/
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inline uint32_t pci_conv_wr_data(uint32_t v1, uint32_t v2, AccessDetails &details)
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{
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{
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switch (details.size << 2 | details.offset) {
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switch (details.size << 2 | details.offset) {
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// Bytes
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// Bytes
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@ -136,7 +136,7 @@ uint32_t MPC106::pci_read(uint32_t offset, uint32_t size) {
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details.size = size;
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details.size = size;
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details.flags = PCI_CONFIG_TYPE_0 | PCI_CONFIG_READ;
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details.flags = PCI_CONFIG_TYPE_0 | PCI_CONFIG_READ;
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uint32_t result = this->dev_map[dev_num]->pci_cfg_read(reg_offs, details);
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uint32_t result = this->dev_map[dev_num]->pci_cfg_read(reg_offs, details);
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return pci_cfg_rev_read(result, details);
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return pci_conv_rd_data(result, details);
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} else {
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} else {
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LOG_F(ERROR, "%s: read attempt from non-existing PCI device ??:%02x.%x @%02x",
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LOG_F(ERROR, "%s: read attempt from non-existing PCI device ??:%02x.%x @%02x",
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this->name.c_str(), dev_num, fun_num, offset);
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this->name.c_str(), dev_num, fun_num, offset);
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@ -167,7 +167,7 @@ void MPC106::pci_write(uint32_t offset, uint32_t value, uint32_t size) {
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this->dev_map[dev_num]->pci_cfg_write(reg_offs, BYTESWAP_32(value), details);
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this->dev_map[dev_num]->pci_cfg_write(reg_offs, BYTESWAP_32(value), details);
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} else { // otherwise perform necessary data transformations -> slow path
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} else { // otherwise perform necessary data transformations -> slow path
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uint32_t old_val = this->dev_map[dev_num]->pci_cfg_read(reg_offs, details);
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uint32_t old_val = this->dev_map[dev_num]->pci_cfg_read(reg_offs, details);
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uint32_t new_val = pci_cfg_rev_write(old_val, value, details);
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uint32_t new_val = pci_conv_wr_data(old_val, value, details);
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this->dev_map[dev_num]->pci_cfg_write(reg_offs, new_val, details);
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this->dev_map[dev_num]->pci_cfg_write(reg_offs, new_val, details);
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}
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}
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} else {
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} else {
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