Macintosh-Tools/dingusppc
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More tests, more fixes

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Only significant bugs left are with stfd(u) and sllq(.)
This commit is contained in:
dingusdev 2020-02-15 11:29:03 -07:00
parent 4f02a98c2b
commit ef27fcec69
2 changed files with 85 additions and 44 deletions
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53
cpu/ppc/ppcdisasm.cpp
View File

@ -56,9 +56,9 @@ const char* bcctrx_cond[8] = { /* simplified branch conditions */
};
const char* opc_idx_ldst[32] = { /* indexed load/store opcodes */
"lwzx", "lwzux", "lbzx", "lbzux", "stwx", "stwux", "stbx", "stbux",
"lhzx", "lhzux", "lhax", "lhaux", "sthx", "sthux", "", "",
"lfsx", "lfsux", "lfdx", "lfdux", "stfsx", "stfsux", "stfdx", "stfdux",
"lwzx", "lwzux", "lbzx", "lbzux", "stwx", "stwux", "stbx", "stbux",
"lhzx", "lhzux", "lhax", "lhaux", "sthx", "sthux", "", "",
"lfsx", "lfsux", "lfdx", "lfdux", "stfsx", "stfsux", "stfdx", "stfdux",
"", "", "", "", "", "", "stfiwx", ""
};
@ -174,7 +174,7 @@ void fmt_threeop_crb(string& buf, const char* opc, int dst, int src1, int src2)
void fmt_threeop_uimm(string& buf, const char* opc, int dst, int src1, int imm)
{
buf = my_sprintf("%-8sr%d, r%d, 0x%04X", opc, dst, src1, imm);
buf = my_sprintf("%-8sr%d, r%d, 0x%X", opc, dst, src1, imm);
}
void fmt_threeop_simm(string& buf, const char* opc, int dst, int src1, int imm)
@ -221,12 +221,12 @@ void opc_twi(PPCDisasmContext* ctx)
if (strlen(opcode) > 0) {
strcat(opcode, "i");
ctx->instr_str = my_sprintf("%-8sr%d, 0x%08X", opcode, ra, imm);
ctx->instr_str = my_sprintf("%-8sr%d, 0x%X", opcode, ra, imm);
return;
}
}
ctx->instr_str = my_sprintf("%-8s%d, r%d, 0x%08X", "twi", to, ra, imm);
ctx->instr_str = my_sprintf("%-8s%d, r%d, 0x%X", "twi", to, ra, imm);
}
void opc_group4(PPCDisasmContext* ctx)
@ -325,7 +325,7 @@ void opc_rlwinm(PPCDisasmContext* ctx)
return;
}
if (me > 0){
if (me > 0) {
ctx->instr_str = my_sprintf("%-8sr%d, r%d, %d, %d", "extlwi", rs, ra, sh, me);
return;
}
@ -343,14 +343,14 @@ void opc_rlmi(PPCDisasmContext* ctx)
{
auto rs = (ctx->instr_code >> 21) & 0x1F;
auto ra = (ctx->instr_code >> 16) & 0x1F;
auto sh = (ctx->instr_code >> 11) & 0x1F;
auto rb = (ctx->instr_code >> 11) & 0x1F;
auto mb = (ctx->instr_code >> 6) & 0x1F;
auto me = (ctx->instr_code >> 1) & 0x1F;
if (ctx->instr_code & 1)
fmt_rotateop(ctx->instr_str, "rlmi.", ra, rs, sh, mb, me, true);
fmt_rotateop(ctx->instr_str, "rlmi.", ra, rs, rb, mb, me, false);
else
fmt_rotateop(ctx->instr_str, "rlmi", ra, rs, sh, mb, me, true);
fmt_rotateop(ctx->instr_str, "rlmi", ra, rs, rb, mb, me, false);
}
void opc_rlwnm(PPCDisasmContext* ctx)
@ -387,7 +387,7 @@ void opc_cmp_i_li(PPCDisasmContext* ctx)
auto imm = ctx->instr_code & 0xFFFF;
if ((ctx->instr_code >> 26) & 0x1)
ctx->instr_str = my_sprintf("%-8scr%d, %d, r%d, 0x%04X", "cmpi", crfd, ls, ra, imm);
ctx->instr_str = my_sprintf("%-8scr%d, %d, r%d, 0x%X", "cmpi", crfd, ls, ra, imm);
else
ctx->instr_str = my_sprintf("%-8scr%d, %d, r%d, 0x%04X", "cmpli", crfd, ls, ra, imm);
}
@ -794,16 +794,15 @@ void opc_group31(PPCDisasmContext* ctx)
strcat(opcode, ".");
switch (index) {
case 0: case 4: case 6: case 16:
case 20: case 22: case 24: case 28:
if ((index == 0) | (index == 4) | (index == 6) | (index == 16) \
| (index == 20) | (index == 22) | (index == 24) | (index == 28)) {
fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
break;
case 5: case 7: case 21: case 23:
case 25: case 29:
}
else if ((index == 5) | (index == 7) | (index == 21) \
| (index == 23) | (index == 25) | (index == 29)) {
fmt_threeop_simm(ctx->instr_str, opcode, ra, rs, rb);
break;
default:
}
else {
opc_illegal(ctx);
}
@ -815,11 +814,11 @@ void opc_group31(PPCDisasmContext* ctx)
if (rc_set)
strcat(opcode, ".");
switch (index) {
case 4: case 6: case 16:
case 20: case 22: case 28:
fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
default:
if ((index == 4) | (index == 6) | (index == 16) \
| (index == 20) | (index == 22) | (index == 28)){
fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
}
else{
opc_illegal(ctx);
}
@ -882,7 +881,7 @@ void opc_group31(PPCDisasmContext* ctx)
fmt_threeop(ctx->instr_str, opc_idx_ldst[index], rs, ra, rb);
}
else {
ctx->instr_str = my_sprintf("%-8sfp%d, r%d, r%d", \
ctx->instr_str = my_sprintf("%-8sf%d, r%d, r%d", \
opc_idx_ldst[index], rs, ra, rb);
}
return;
@ -890,7 +889,7 @@ void opc_group31(PPCDisasmContext* ctx)
case 0x16: /* processor mgmt + byte reversed load and store instructions */
strcpy(opcode, proc_mgmt_str[index]);
if (index == 4){ /* stwcx.*/
if (index == 4) { /* stwcx.*/
if (!rc_set) {
opc_illegal(ctx);
return;
@ -1647,4 +1646,4 @@ string disassemble_single(PPCDisasmContext* ctx)
ctx->instr_addr += 4;
return ctx->instr_str;
}
}

76
cpu/ppc/test/ppcdisasmtest.csv
View File

@ -77,14 +77,6 @@
0xFFF00100,0x7C98DAEE,lhaux,r4,r24,r27
0xFFF00100,0x7C0C0B2E,sthx,r0,r12,r1
0xFFF00100,0x7C032B6E,sthux,r0,r3,r5
0xFFF00100,0x7C43242E,lfsx,fp2,r3,r4
0xFFF00100,0x7C43246E,lfsux,fp2,r3,r4
0xFFF00100,0x7D491CAE,lfdx,fp10,r9,r3
0xFFF00100,0x7C4324EE,lfdux,fp2,r3,r4
0xFFF00100,0x7C43252E,stfsx,fp2,r3,r4
0xFFF00100,0x7C43256E,stfsux,fp2,r3,r4
0xFFF00100,0x7C4325AE,stfdx,fp2,r3,r4
0xFFF00100,0x7C4325EE,stfdux,fp2,r3,r4
# arithmetic instructions with immediate operand
0xFFF00100,0x1F00A81A,mulli,r24,r0,-0x57E6
@ -164,20 +156,20 @@
0xFFF00100,0x7CA72097,mulhw.,r5,r7,r4
0xFFF00100,0x7C9000D6,mul,r4,r16,r0
0xFFF00100,0x7CA428D7,mul.,r5,r4,r5
# FIXME mulo
# FIXME mulo.
0xFFF00100,0x7E1104D6,mulo,r16,r17,r0
0xFFF00100,0x7E1104D7,mulo.,r16,r17,r0
0xFFF00100,0x7D0039D6,mullw,r8,r0,r7
0xFFF00100,0x7C1DF1D7,mullw.,r0,r29,r30
0xFFF00100,0x7CE725D6,mullwo,r7,r7,r4
0xFFF00100,0x7CE725D7,mullwo.,r7,r7,r4
0xFFF00100,0x7FEB2296,div,r31,r11,r4
0xFFF00100,0x7C064297,div.,r0,r6,r8
# FIXME divo
# FIXME divo.
0xFFF00100,0x7DE70696,divo,r15,r7,r0
0xFFF00100,0x7DE70697,divo.,r15,r7,r0
0xFFF00100,0x7CA03AD6,divs,r5,r0,r7
0xFFF00100,0x7C642AD7,divs.,r3,r4,r5
# FIXME divso
# FIXME divso.
0xFFF00100,0x7F0106D6,divso,r24,r1,r0
0xFFF00100,0x7F0106D7,divso.,r24,r1,r0
0xFFF00100,0x7F7C1B96,divwu,r27,r28,r3
0xFFF00100,0x7C7B1B97,divwu.,r3,r27,r3
0xFFF00100,0x7CE62796,divwuo,r7,r6,r4
@ -229,9 +221,14 @@
#logical immediate instructions
0xFFF00100,0x60009BA5,ori,r0,r0,0x9BA5
0xFFF00100,0x6744AAAA,oris,r4,r26,0xAAAA
0xFFF00100,0x6B24002D,xori,r4,r25,0x2D
0xFFF00100,0x6C602003,xoris,r0,r3,0x2003
0xFFF00100,0x70410022,andi.,r1,r2,0x22
0xFFF00100,0x7541029E,andis.,r1,r10,0x29E
# synchronization instructions
0xFFF00100,0x7FEF2E2C,lhbrx,r31,r15,r5
0xFFF00100,0x7C604C2C,lwbrx,r3,0,r9
0xFFF00100,0x7D201828,lwarx,r9,0,r3
0xFFF00100,0x7D20192D,stwcx.,r9,0,r3
0xFFF00100,0x7FAB052C,stwbrx,r29,r11,r0
@ -242,7 +239,7 @@
# trap instructions
0xFFF00100,0x7F800008,tw,28,r0,r0
0xFFF00100,0x0C000000,twi,0,r0,0
0xFFF00100,0x0C000000,twi,0,r0,0x0
# integer load and stores
0xFFF00100,0x80BF0808,lwz,r5,0x808(r31)
@ -281,7 +278,33 @@
0xFFF00100,0xBB41FFE8,lmw,r26,-0x18(r1)
0xFFF00100,0xBC410008,stmw,r2,0x8(r1)
0xFFF00100,0xBFC1FFF8,stmw,r30,-0x8(r1)
0xFFF00100,0xD58B0004,stfsu,f12,4(r11)
#floating point load and stores
0xFFF00100,0x7C0BF5AE,stfdx,f0,r11,r30
0xFFF00100,0x7C0525EE,stfdux,f0,r5,r4
0xFFF00100,0x7D89FD2E,stfsx,f12,r9,r31
0xFFF00100,0x7D59FD6E,stfsux,f10,r25,r31
0xFFF00100,0xC80100C8,lfd,f0,0xC8(r1)
0xFFF00100,0xCC1F0008,lfdu,f0,0x8(r31)
0xFFF00100,0xC1628398,lfs,f11,-0x7C68(r2)
0xFFF00100,0xC5BE0004,lfsu,f13,0x4(r30)
0xFFF00100,0xDBC1FFF0,stfd,f30,-0x10(r1)
0xFFF00100,0xD8010860,stfd,f0,0x860(r1)
0xFFF00100,0xDC180008,stfdu,f0,0x8(r24)
0xFFF00100,0xD01E0110,stfs,f0,0x110(r30)
0xFFF00100,0xD58B0004,stfsu,f12,0x4(r11)
0xFFF00100,0x7C1C5CAE,lfdx,f0,r28,r11
0xFFF00100,0x7CAA7CEE,lfdux,f5,r10,r15
0xFFF00100,0x7FEF2C6E,lfsux,f31,r15,r5
0xFFF00100,0x7C09DC2E,lfsx,f0,r9,r27
0xFFF00100,0x7C43242E,lfsx,f2,r3,r4
0xFFF00100,0x7C43246E,lfsux,f2,r3,r4
0xFFF00100,0x7D491CAE,lfdx,f10,r9,r3
0xFFF00100,0x7C4324EE,lfdux,f2,r3,r4
0xFFF00100,0x7C43252E,stfsx,f2,r3,r4
0xFFF00100,0x7C43256E,stfsux,f2,r3,r4
0xFFF00100,0x7C4325AE,stfdx,f2,r3,r4
0xFFF00100,0x7C4325EE,stfdux,f2,r3,r4
#floating point operations
0xFFF00100,0xFC03282A,fadd,f0,f3,f5
@ -343,4 +366,23 @@
0xFFF00100,0x7C440426,clcs,r2,r4
0xFFF00100,0x24000800,dozi,r0,r0,0x800
0xFFF00100,0x7C00003A,maskg,r0,r0,r0
0xFFF00100,0x7E3EE43A,maskir,r30,r17,r28
0xFFF00100,0x7E3EE43A,maskir,r30,r17,r28
0xFFF00100,0x58411800,rlmi,r1,r2,r3,0,0
0xFFF00100,0x58411801,rlmi.,r1,r2,r3,0,0
0xFFF00100,0x7C430C32,rrib,r3,r2,r1
0xFFF00100,0x7C430C33,rrib.,r3,r2,r1
0xFFF00100,0x7C410132,sle,r1,r2,r0
0xFFF00100,0x7C410133,sle.,r1,r2,r0
0xFFF00100,0x7C4101B2,sleq,r1,r2,r0
0xFFF00100,0x7C4101B3,sleq.,r1,r2,r0
0xFFF00100,0x7C811970,sliq,r1,r4,0x3
0xFFF00100,0x7C4101F0,slliq,r1,r2,0x0
0xFFF00100,0x7C4101F1,slliq.,r1,r2,0x0
0xFFF00100,0x7C10242C,sllq,r16,r0,r4
0xFFF00100,0x7C10242D,sllq.,r16,r0,r4
0xFFF00100,0x7C410532,sre,r1,r2,r0
0xFFF00100,0x7C410533,sre.,r1,r2,r0
0xFFF00100,0x7C4105B2,sreq,r1,r2,r0
0xFFF00100,0x7C4105B3,sreq.,r1,r2,r0
0xFFF00100,0x7E042570,sriq,r4,r16,0x4
0xFFF00100,0x7E042571,sriq.,r4,r16,0x4
1 # Test data for PowerPC disassembler supplied as comma-separated values
77 0xFFF00100,0x7D491CAE,lfdx,fp10,r9,r3 0xFFF00100,0x1D8A4CCC,mulli,r12,r10,0x4CCC
78 0xFFF00100,0x7C4324EE,lfdux,fp2,r3,r4 0xFFF00100,0x207CFEE0,subfic,r3,r28,-0x120
79 0xFFF00100,0x7C43252E,stfsx,fp2,r3,r4 0xFFF00100,0x20894E75,subfic,r4,r9,0x4E75
0xFFF00100,0x7C43256E,stfsux,fp2,r3,r4
0xFFF00100,0x7C4325AE,stfdx,fp2,r3,r4
0xFFF00100,0x7C4325EE,stfdux,fp2,r3,r4
# arithmetic instructions with immediate operand
0xFFF00100,0x1F00A81A,mulli,r24,r0,-0x57E6
0xFFF00100,0x1D8A4CCC,mulli,r12,r10,0x4CCC
0xFFF00100,0x207CFEE0,subfic,r3,r28,-0x120
0xFFF00100,0x20894E75,subfic,r4,r9,0x4E75
80 0xFFF00100,0x38BE0000,addi,r5,r30,0x0
81 0xFFF00100,0x3A2EFFF0,addi,r17,r14,-0x10
82 0xFFF00100,0x307F005E,addic,r3,r31,0x5E
156 0xFFF00100,0x7FEB2296,div,r31,r11,r4
157 0xFFF00100,0x7C064297,div.,r0,r6,r8
158 # FIXME divo 0xFFF00100,0x7DE70696,divo,r15,r7,r0
159 # FIXME divo. 0xFFF00100,0x7DE70697,divo.,r15,r7,r0
160 0xFFF00100,0x7CA03AD6,divs,r5,r0,r7
161 0xFFF00100,0x7C642AD7,divs.,r3,r4,r5
162 # FIXME divso 0xFFF00100,0x7F0106D6,divso,r24,r1,r0
163 # FIXME divso. 0xFFF00100,0x7F0106D7,divso.,r24,r1,r0
164 0xFFF00100,0x7F7C1B96,divwu,r27,r28,r3
165 0xFFF00100,0x7C7B1B97,divwu.,r3,r27,r3
166 0xFFF00100,0x7CE62796,divwuo,r7,r6,r4
167 0xFFF00100,0x7CE62797,divwuo.,r7,r6,r4
168 0xFFF00100,0x7C042BD6,divw,r0,r4,r5
169 0xFFF00100,0x7C042BD7,divw.,r0,r4,r5
170 0xFFF00100,0x7CA627D6,divwo,r5,r6,r4
171 0xFFF00100,0x7CA627D7,divwo.,r5,r6,r4
172 # move to condition register, primary opcode 0x1F
173 0xFFF00100,0x7D818120,mtcrf,0x18,r12
174 0xFFF00100,0x7D838120,mtcrf,0x38,r12
175 0xFFF00100,0x7D080120,mtcrf,0x80,r8
221 0xFFF00100,0x0C000000,twi,0,r0,0 0xFFF00100,0x7C0004AC,sync
222 # integer load and stores 0xFFF00100,0x7C0006AC,eieio
223 0xFFF00100,0x80BF0808,lwz,r5,0x808(r31) 0xFFF00100,0x7C05272C,sthbrx,r0,r5,r4
224 # trap instructions
225 0xFFF00100,0x7F800008,tw,28,r0,r0
226 0xFFF00100,0x0C000000,twi,0,r0,0x0
227 # integer load and stores
228 0xFFF00100,0x80A2FFB8,lwz,r5,-0x48(r2) 0xFFF00100,0x80BF0808,lwz,r5,0x808(r31)
229 0xFFF00100,0x80002F3C,lwz,r0,0x2F3C 0xFFF00100,0x80A2FFB8,lwz,r5,-0x48(r2)
230 0xFFF00100,0x8506003C,lwzu,r8,0x3C(r6) 0xFFF00100,0x80002F3C,lwz,r0,0x2F3C
231 0xFFF00100,0x8506003C,lwzu,r8,0x3C(r6)
232 0xFFF00100,0x8403FFF8,lwzu,r0,-0x8(r3)
233 0xFFF00100,0x88FD00FA,lbz,r7,0xFA(r29)
234 0xFFF00100,0x889EFFF4,lbz,r4,-0xC(r30)
239 0xFFF00100,0x9146696E,stw,r10,0x696E(r6)
240 0xFFF00100,0x9317FFF0,stw,r24,-0x10(r23)
241 0xFFF00100,0x94050020,stwu,r0,0x20(r5)
242 0xFFF00100,0x9421FFA0,stwu,r1,-0x60(r1)
243 0xFFF00100,0x981F00FA,stb,r0,0xFA(r31)
244 0xFFF00100,0x98829882,stb,r4,-0x677E(r2)
245 0xFFF00100,0x9EFC000A,stbu,r23,0xA(r28)
278 0xFFF00100,0xFD600110,fnabs,f11,f0 0xFFF00100,0x7C1C5CAE,lfdx,f0,r28,r11
279 0xFFF00100,0xFD002034,frsqrte,f8,f4 0xFFF00100,0x7CAA7CEE,lfdux,f5,r10,r15
280 0xFFF00100,0x7FF957AE,stfiwx,f31,r25,r10 0xFFF00100,0x7FEF2C6E,lfsux,f31,r15,r5
281 #compare instructions 0xFFF00100,0x7C09DC2E,lfsx,f0,r9,r27
282 0xFFF00100,0x7C43242E,lfsx,f2,r3,r4
283 0xFFF00100,0x7C43246E,lfsux,f2,r3,r4
284 0xFFF00100,0x7D491CAE,lfdx,f10,r9,r3
285 0xFFF00100,0x7C4324EE,lfdux,f2,r3,r4
286 0xFFF00100,0x7C43252E,stfsx,f2,r3,r4
287 0xFFF00100,0x7C43256E,stfsux,f2,r3,r4
288 0xFFF00100,0x7C4325AE,stfdx,f2,r3,r4
289 0xFFF00100,0x7C4325EE,stfdux,f2,r3,r4
290 #floating point operations
291 0xFFF00100,0xFC03282A,fadd,f0,f3,f5
292 0xFFF00100,0xFDAD682B,fadd.,f13,f13,f13
293 0xFFF00100,0xFC0D6028,fsub,f0,f13,f12
294 0xFFF00100,0xFC2107F2,fmul,f1,f1,f31
295 0xFFF00100,0xFF2C07F3,fmul.,f25,f12,f31
296 0xFFF00100,0xFC0D0024,fdiv,f0,f13,f0
297 0xFFF00100,0xFC2B0025,fdiv.,f1,f11,f0
298 0xFFF00100,0xFD8952FC,fnmsub,f12,f9,f11,f10
299 0xFFF00100,0xEDA66278,fmsubs,f13,f6,f9,f12
300 0xFFF00100,0xEDA66279,fmsubs.,f13,f6,f9,f12
301 0xFFF00100,0xEC00637C,fnmsubs,f0,f0,f13,f12
302 0xFFF00100,0xFE0820AF,fsel.,f16,f8,f2,f4
303 0xFFF00100,0xFD600110,fnabs,f11,f0
304 0xFFF00100,0xFD002034,frsqrte,f8,f4
305 0xFFF00100,0x7FF957AE,stfiwx,f31,r25,r10
306 #compare instructions
307 0xFFF00100,0x7FBFB800,cmp,cr7,1,r31,r23
308 0xFFF00100,0x7FBFB800,cmp,cr7,1,r31,r23 0xFFF00100,0x7FA05840,cmpl,cr7,1,r0,r11
309 0xFFF00100,0x7FA05840,cmpl,cr7,1,r0,r11 0xFFF00100,0x2FA90000,cmpi,cr7,1,r9,0x0
310 0xFFF00100,0x2FA90000,cmpi,cr7,1,r9,0x0 0xFFF00100,0x2AA3FFFF,cmpli,cr5,1,r3,0xFFFF
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