mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-12-23 21:29:28 +00:00
More tests, more fixes
Only significant bugs left are with stfd(u) and sllq(.)
This commit is contained in:
dingusdev
parent
4f02a98c2b
commit
ef27fcec69
@ -174,7 +174,7 @@ void fmt_threeop_crb(string& buf, const char* opc, int dst, int src1, int src2)
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void fmt_threeop_uimm(string& buf, const char* opc, int dst, int src1, int imm)
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{
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buf = my_sprintf("%-8sr%d, r%d, 0x%04X", opc, dst, src1, imm);
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buf = my_sprintf("%-8sr%d, r%d, 0x%X", opc, dst, src1, imm);
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}
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void fmt_threeop_simm(string& buf, const char* opc, int dst, int src1, int imm)
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@ -221,12 +221,12 @@ void opc_twi(PPCDisasmContext* ctx)
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if (strlen(opcode) > 0) {
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strcat(opcode, "i");
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ctx->instr_str = my_sprintf("%-8sr%d, 0x%08X", opcode, ra, imm);
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ctx->instr_str = my_sprintf("%-8sr%d, 0x%X", opcode, ra, imm);
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return;
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}
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}
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ctx->instr_str = my_sprintf("%-8s%d, r%d, 0x%08X", "twi", to, ra, imm);
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ctx->instr_str = my_sprintf("%-8s%d, r%d, 0x%X", "twi", to, ra, imm);
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}
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void opc_group4(PPCDisasmContext* ctx)
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@ -325,7 +325,7 @@ void opc_rlwinm(PPCDisasmContext* ctx)
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return;
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}
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if (me > 0){
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if (me > 0) {
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ctx->instr_str = my_sprintf("%-8sr%d, r%d, %d, %d", "extlwi", rs, ra, sh, me);
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return;
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}
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@ -343,14 +343,14 @@ void opc_rlmi(PPCDisasmContext* ctx)
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{
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auto rs = (ctx->instr_code >> 21) & 0x1F;
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auto ra = (ctx->instr_code >> 16) & 0x1F;
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auto sh = (ctx->instr_code >> 11) & 0x1F;
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auto rb = (ctx->instr_code >> 11) & 0x1F;
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auto mb = (ctx->instr_code >> 6) & 0x1F;
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auto me = (ctx->instr_code >> 1) & 0x1F;
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if (ctx->instr_code & 1)
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fmt_rotateop(ctx->instr_str, "rlmi.", ra, rs, sh, mb, me, true);
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fmt_rotateop(ctx->instr_str, "rlmi.", ra, rs, rb, mb, me, false);
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else
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fmt_rotateop(ctx->instr_str, "rlmi", ra, rs, sh, mb, me, true);
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fmt_rotateop(ctx->instr_str, "rlmi", ra, rs, rb, mb, me, false);
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}
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void opc_rlwnm(PPCDisasmContext* ctx)
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@ -387,7 +387,7 @@ void opc_cmp_i_li(PPCDisasmContext* ctx)
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auto imm = ctx->instr_code & 0xFFFF;
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if ((ctx->instr_code >> 26) & 0x1)
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ctx->instr_str = my_sprintf("%-8scr%d, %d, r%d, 0x%04X", "cmpi", crfd, ls, ra, imm);
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ctx->instr_str = my_sprintf("%-8scr%d, %d, r%d, 0x%X", "cmpi", crfd, ls, ra, imm);
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else
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ctx->instr_str = my_sprintf("%-8scr%d, %d, r%d, 0x%04X", "cmpli", crfd, ls, ra, imm);
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}
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@ -794,16 +794,15 @@ void opc_group31(PPCDisasmContext* ctx)
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strcat(opcode, ".");
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switch (index) {
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case 0: case 4: case 6: case 16:
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case 20: case 22: case 24: case 28:
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if ((index == 0) | (index == 4) | (index == 6) | (index == 16) \
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| (index == 20) | (index == 22) | (index == 24) | (index == 28)) {
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fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
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break;
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case 5: case 7: case 21: case 23:
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case 25: case 29:
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}
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else if ((index == 5) | (index == 7) | (index == 21) \
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| (index == 23) | (index == 25) | (index == 29)) {
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fmt_threeop_simm(ctx->instr_str, opcode, ra, rs, rb);
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break;
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default:
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}
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else {
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opc_illegal(ctx);
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}
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@ -815,11 +814,11 @@ void opc_group31(PPCDisasmContext* ctx)
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if (rc_set)
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strcat(opcode, ".");
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switch (index) {
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case 4: case 6: case 16:
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case 20: case 22: case 28:
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fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
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default:
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if ((index == 4) | (index == 6) | (index == 16) \
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| (index == 20) | (index == 22) | (index == 28)){
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fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
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}
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else{
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opc_illegal(ctx);
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}
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@ -882,7 +881,7 @@ void opc_group31(PPCDisasmContext* ctx)
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fmt_threeop(ctx->instr_str, opc_idx_ldst[index], rs, ra, rb);
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}
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else {
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ctx->instr_str = my_sprintf("%-8sfp%d, r%d, r%d", \
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ctx->instr_str = my_sprintf("%-8sf%d, r%d, r%d", \
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opc_idx_ldst[index], rs, ra, rb);
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}
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return;
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@ -890,7 +889,7 @@ void opc_group31(PPCDisasmContext* ctx)
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case 0x16: /* processor mgmt + byte reversed load and store instructions */
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strcpy(opcode, proc_mgmt_str[index]);
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if (index == 4){ /* stwcx.*/
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if (index == 4) { /* stwcx.*/
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if (!rc_set) {
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opc_illegal(ctx);
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return;
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@ -77,14 +77,6 @@
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0xFFF00100,0x7C98DAEE,lhaux,r4,r24,r27
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0xFFF00100,0x7C0C0B2E,sthx,r0,r12,r1
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0xFFF00100,0x7C032B6E,sthux,r0,r3,r5
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0xFFF00100,0x7C43242E,lfsx,fp2,r3,r4
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0xFFF00100,0x7C43246E,lfsux,fp2,r3,r4
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0xFFF00100,0x7D491CAE,lfdx,fp10,r9,r3
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0xFFF00100,0x7C4324EE,lfdux,fp2,r3,r4
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0xFFF00100,0x7C43252E,stfsx,fp2,r3,r4
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0xFFF00100,0x7C43256E,stfsux,fp2,r3,r4
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0xFFF00100,0x7C4325AE,stfdx,fp2,r3,r4
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0xFFF00100,0x7C4325EE,stfdux,fp2,r3,r4
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# arithmetic instructions with immediate operand
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0xFFF00100,0x1F00A81A,mulli,r24,r0,-0x57E6
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@ -164,20 +156,20 @@
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0xFFF00100,0x7CA72097,mulhw.,r5,r7,r4
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0xFFF00100,0x7C9000D6,mul,r4,r16,r0
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0xFFF00100,0x7CA428D7,mul.,r5,r4,r5
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# FIXME mulo
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# FIXME mulo.
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0xFFF00100,0x7E1104D6,mulo,r16,r17,r0
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0xFFF00100,0x7E1104D7,mulo.,r16,r17,r0
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0xFFF00100,0x7D0039D6,mullw,r8,r0,r7
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0xFFF00100,0x7C1DF1D7,mullw.,r0,r29,r30
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0xFFF00100,0x7CE725D6,mullwo,r7,r7,r4
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0xFFF00100,0x7CE725D7,mullwo.,r7,r7,r4
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0xFFF00100,0x7FEB2296,div,r31,r11,r4
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0xFFF00100,0x7C064297,div.,r0,r6,r8
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# FIXME divo
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# FIXME divo.
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0xFFF00100,0x7DE70696,divo,r15,r7,r0
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0xFFF00100,0x7DE70697,divo.,r15,r7,r0
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0xFFF00100,0x7CA03AD6,divs,r5,r0,r7
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0xFFF00100,0x7C642AD7,divs.,r3,r4,r5
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# FIXME divso
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# FIXME divso.
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0xFFF00100,0x7F0106D6,divso,r24,r1,r0
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0xFFF00100,0x7F0106D7,divso.,r24,r1,r0
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0xFFF00100,0x7F7C1B96,divwu,r27,r28,r3
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0xFFF00100,0x7C7B1B97,divwu.,r3,r27,r3
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0xFFF00100,0x7CE62796,divwuo,r7,r6,r4
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@ -229,9 +221,14 @@
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#logical immediate instructions
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0xFFF00100,0x60009BA5,ori,r0,r0,0x9BA5
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0xFFF00100,0x6744AAAA,oris,r4,r26,0xAAAA
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0xFFF00100,0x6B24002D,xori,r4,r25,0x2D
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0xFFF00100,0x6C602003,xoris,r0,r3,0x2003
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0xFFF00100,0x70410022,andi.,r1,r2,0x22
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0xFFF00100,0x7541029E,andis.,r1,r10,0x29E
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# synchronization instructions
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0xFFF00100,0x7FEF2E2C,lhbrx,r31,r15,r5
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0xFFF00100,0x7C604C2C,lwbrx,r3,0,r9
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0xFFF00100,0x7D201828,lwarx,r9,0,r3
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0xFFF00100,0x7D20192D,stwcx.,r9,0,r3
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0xFFF00100,0x7FAB052C,stwbrx,r29,r11,r0
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@ -242,7 +239,7 @@
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# trap instructions
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0xFFF00100,0x7F800008,tw,28,r0,r0
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0xFFF00100,0x0C000000,twi,0,r0,0
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0xFFF00100,0x0C000000,twi,0,r0,0x0
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# integer load and stores
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0xFFF00100,0x80BF0808,lwz,r5,0x808(r31)
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@ -281,7 +278,33 @@
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0xFFF00100,0xBB41FFE8,lmw,r26,-0x18(r1)
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0xFFF00100,0xBC410008,stmw,r2,0x8(r1)
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0xFFF00100,0xBFC1FFF8,stmw,r30,-0x8(r1)
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0xFFF00100,0xD58B0004,stfsu,f12,4(r11)
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#floating point load and stores
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0xFFF00100,0x7C0BF5AE,stfdx,f0,r11,r30
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0xFFF00100,0x7C0525EE,stfdux,f0,r5,r4
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0xFFF00100,0x7D89FD2E,stfsx,f12,r9,r31
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0xFFF00100,0x7D59FD6E,stfsux,f10,r25,r31
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0xFFF00100,0xC80100C8,lfd,f0,0xC8(r1)
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0xFFF00100,0xCC1F0008,lfdu,f0,0x8(r31)
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0xFFF00100,0xC1628398,lfs,f11,-0x7C68(r2)
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0xFFF00100,0xC5BE0004,lfsu,f13,0x4(r30)
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0xFFF00100,0xDBC1FFF0,stfd,f30,-0x10(r1)
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0xFFF00100,0xD8010860,stfd,f0,0x860(r1)
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0xFFF00100,0xDC180008,stfdu,f0,0x8(r24)
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0xFFF00100,0xD01E0110,stfs,f0,0x110(r30)
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0xFFF00100,0xD58B0004,stfsu,f12,0x4(r11)
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0xFFF00100,0x7C1C5CAE,lfdx,f0,r28,r11
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0xFFF00100,0x7CAA7CEE,lfdux,f5,r10,r15
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0xFFF00100,0x7FEF2C6E,lfsux,f31,r15,r5
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0xFFF00100,0x7C09DC2E,lfsx,f0,r9,r27
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0xFFF00100,0x7C43242E,lfsx,f2,r3,r4
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0xFFF00100,0x7C43246E,lfsux,f2,r3,r4
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0xFFF00100,0x7D491CAE,lfdx,f10,r9,r3
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0xFFF00100,0x7C4324EE,lfdux,f2,r3,r4
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0xFFF00100,0x7C43252E,stfsx,f2,r3,r4
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0xFFF00100,0x7C43256E,stfsux,f2,r3,r4
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0xFFF00100,0x7C4325AE,stfdx,f2,r3,r4
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0xFFF00100,0x7C4325EE,stfdux,f2,r3,r4
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#floating point operations
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0xFFF00100,0xFC03282A,fadd,f0,f3,f5
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@ -344,3 +367,22 @@
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0xFFF00100,0x24000800,dozi,r0,r0,0x800
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0xFFF00100,0x7C00003A,maskg,r0,r0,r0
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0xFFF00100,0x7E3EE43A,maskir,r30,r17,r28
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0xFFF00100,0x58411800,rlmi,r1,r2,r3,0,0
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0xFFF00100,0x58411801,rlmi.,r1,r2,r3,0,0
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0xFFF00100,0x7C430C32,rrib,r3,r2,r1
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0xFFF00100,0x7C430C33,rrib.,r3,r2,r1
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0xFFF00100,0x7C410132,sle,r1,r2,r0
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0xFFF00100,0x7C410133,sle.,r1,r2,r0
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0xFFF00100,0x7C4101B2,sleq,r1,r2,r0
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0xFFF00100,0x7C4101B3,sleq.,r1,r2,r0
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0xFFF00100,0x7C811970,sliq,r1,r4,0x3
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0xFFF00100,0x7C4101F0,slliq,r1,r2,0x0
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0xFFF00100,0x7C4101F1,slliq.,r1,r2,0x0
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0xFFF00100,0x7C10242C,sllq,r16,r0,r4
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0xFFF00100,0x7C10242D,sllq.,r16,r0,r4
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0xFFF00100,0x7C410532,sre,r1,r2,r0
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0xFFF00100,0x7C410533,sre.,r1,r2,r0
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0xFFF00100,0x7C4105B2,sreq,r1,r2,r0
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0xFFF00100,0x7C4105B3,sreq.,r1,r2,r0
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0xFFF00100,0x7E042570,sriq,r4,r16,0x4
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0xFFF00100,0x7E042571,sriq.,r4,r16,0x4
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