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https://github.com/dingusdev/dingusppc.git
synced 2025-01-10 13:29:38 +00:00
sc53c94: fix interrupt reporting.
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parent
29f3ffd474
commit
f5bb484226
@ -280,7 +280,7 @@ void Sc53C94::exec_command()
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});
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if (!(config1 & 0x40)) {
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LOG_F(INFO, "%s: reset interrupt issued", this->name.c_str());
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this->int_status |= INTSTAT_SRST;
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this->int_status = INTSTAT_SRST;
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}
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exec_next_command();
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break;
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@ -288,7 +288,7 @@ void Sc53C94::exec_command()
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if (!this->is_initiator) {
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// clear command FIFO
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this->cmd_fifo_pos = 0;
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this->int_status |= INTSTAT_ICMD;
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this->int_status = INTSTAT_ICMD;
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this->update_irq();
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} else {
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this->seq_step = 0;
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@ -316,7 +316,7 @@ void Sc53C94::exec_command()
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this->bus_obj->target_next_step();
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}
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this->bus_obj->release_ctrl_line(this->my_bus_id, SCSI_CTRL_ACK);
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this->int_status |= INTSTAT_SR;
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this->int_status = INTSTAT_SR;
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this->int_status |= INTSTAT_DIS; // TODO: handle target disconnection properly
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this->update_irq();
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exec_next_command();
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@ -353,7 +353,7 @@ void Sc53C94::exec_command()
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default:
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LOG_F(ERROR, "%s: invalid/unimplemented command 0x%X", this->name.c_str(), cmd);
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this->cmd_fifo_pos--; // remove invalid command from FIFO
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this->int_status |= INTSTAT_ICMD;
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this->int_status = INTSTAT_ICMD;
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this->update_irq();
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}
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}
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@ -455,7 +455,7 @@ void Sc53C94::sequencer()
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LOG_F(9, "%s: selection completed", this->name.c_str());
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} else { // selection timeout
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this->seq_step = this->cmd_steps->step_num;
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this->int_status |= this->cmd_steps->status;
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this->int_status = this->cmd_steps->status;
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this->bus_obj->disconnect(this->my_bus_id);
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this->cur_state = SeqState::IDLE;
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this->update_irq();
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@ -465,7 +465,7 @@ void Sc53C94::sequencer()
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case SeqState::SEND_MSG:
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if (this->data_fifo_pos < 1 && this->is_dma_cmd) {
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this->drq_cb(1);
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this->int_status |= INTSTAT_SR;
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this->int_status = INTSTAT_SR;
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this->update_irq();
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break;
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}
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@ -482,8 +482,8 @@ void Sc53C94::sequencer()
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this->bus_obj->target_xfer_data();
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break;
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case SeqState::CMD_COMPLETE:
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this->seq_step = this->cmd_steps->step_num;
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this->int_status |= this->cmd_steps->status;
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this->seq_step = this->cmd_steps->step_num;
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this->int_status = this->cmd_steps->status;
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this->update_irq();
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exec_next_command();
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break;
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@ -514,7 +514,7 @@ void Sc53C94::sequencer()
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if (this->is_initiator) {
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this->bus_obj->target_next_step();
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}
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this->int_status |= INTSTAT_SR;
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this->int_status = INTSTAT_SR;
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this->update_irq();
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exec_next_command();
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break;
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@ -524,7 +524,7 @@ void Sc53C94::sequencer()
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// check for unexpected bus phase changes
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if (this->bus_obj->current_phase() != this->cur_bus_phase) {
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this->cmd_fifo_pos = 0; // clear command FIFO
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this->int_status |= INTSTAT_SR;
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this->int_status = INTSTAT_SR;
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this->update_irq();
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} else {
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this->rcv_data();
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@ -216,7 +216,7 @@ private:
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uint32_t set_xfer_count;
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uint8_t status;
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uint8_t target_id;
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uint8_t int_status;
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uint8_t int_status = 0;
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uint8_t seq_step;
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uint8_t sel_timeout;
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uint8_t sync_offset;
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