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https://github.com/dingusdev/dingusppc.git
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dbdma: fix LOAD_QUAD and STORE_QUAD to work with MMIO.
This commit is contained in:
Maxim Poliakovski
parent
8cf290c034
commit
f754f63f8f
@ -38,12 +38,13 @@ void DMAChannel::set_callbacks(DbdmaCallback start_cb, DbdmaCallback stop_cb) {
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/* Load DMACmd from physical memory. */
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void DMAChannel::fetch_cmd(uint32_t cmd_addr, DMACmd* p_cmd) {
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memcpy((uint8_t*)p_cmd, mmu_get_dma_mem(cmd_addr, 16, nullptr), 16);
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MapDmaResult res = mmu_map_dma_mem(cmd_addr, 16, false);
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memcpy((uint8_t*)p_cmd, res.host_va, 16);
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}
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uint8_t DMAChannel::interpret_cmd() {
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DMACmd cmd_struct;
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bool is_writable, branch_taken = false;
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MapDmaResult res;
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if (this->cmd_in_progress) {
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// return current command if there is data to transfer
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@ -68,7 +69,8 @@ uint8_t DMAChannel::interpret_cmd() {
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LOG_F(ERROR, "Key > 0 not implemented");
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break;
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}
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this->queue_data = mmu_get_dma_mem(cmd_struct.address, cmd_struct.req_count, &is_writable);
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res = mmu_map_dma_mem(cmd_struct.address, cmd_struct.req_count, false);
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this->queue_data = res.host_va;
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this->queue_len = cmd_struct.req_count;
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this->cmd_in_progress = true;
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break;
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@ -100,10 +102,11 @@ uint8_t DMAChannel::interpret_cmd() {
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void DMAChannel::finish_cmd() {
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DMACmd cmd_struct;
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bool is_writable, branch_taken = false;
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bool branch_taken = false;
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// obtain real pointer to the descriptor of the command to be finished
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uint8_t *cmd_desc = mmu_get_dma_mem(this->cmd_ptr, 16, &is_writable);
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MapDmaResult res = mmu_map_dma_mem(this->cmd_ptr, 16, false);
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uint8_t *cmd_desc = res.host_va;
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// get command code
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this->cur_cmd = cmd_desc[3] >> 4;
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@ -111,21 +114,32 @@ void DMAChannel::finish_cmd() {
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// all commands except STOP update cmd.xferStatus and
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// perform actions under control of "i", "b" and "w" bits
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if (this->cur_cmd < DBDMA_Cmd::STOP) {
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if (is_writable)
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WRITE_WORD_LE_A(&cmd_desc[14], this->ch_stat | CH_STAT_ACTIVE);
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// react to cmd.w (wait) bits
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if (cmd_desc[2] & 3) {
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ABORT_F("DBDMA: cmd.w bit not implemented");
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bool cond = true;
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if ((cmd_desc[2] & 3) != 3) {
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uint16_t wt_mask = this->wait_select >> 16;
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cond = (this->ch_stat & wt_mask) == (this->wait_select & wt_mask);
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if ((cmd_desc[2] & 3) == 2) {
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cond = !cond; // wait if cond = false
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}
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}
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if (cond)
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return;
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}
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// react to cmd.b bit
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if (res.is_writable)
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WRITE_WORD_LE_A(&cmd_desc[14], this->ch_stat | CH_STAT_ACTIVE);
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// react to cmd.b (branch) bits
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if (cmd_desc[2] & 0xC) {
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bool cond = true;
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if ((cmd_desc[2] & 0xC) != 0xC) {
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uint16_t br_mask = this->branch_select >> 16;
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cond = (this->ch_stat & br_mask) == (this->branch_select & br_mask);
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if ((cmd_desc[2] & 0xC) == 0x8) { // branch if cond cleared?
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cond = !cond;
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if ((cmd_desc[2] & 0xC) == 0x8) {
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cond = !cond; // branch if cond = false
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}
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}
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if (cond) {
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@ -138,7 +152,7 @@ void DMAChannel::finish_cmd() {
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}
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// all INPUT and OUTPUT commands update cmd.resCount
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if (this->cur_cmd < DBDMA_Cmd::STORE_QUAD && is_writable) {
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if (this->cur_cmd < DBDMA_Cmd::STORE_QUAD && res.is_writable) {
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WRITE_WORD_LE_A(&cmd_desc[12], this->queue_len & 0xFFFFUL);
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}
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@ -149,8 +163,9 @@ void DMAChannel::finish_cmd() {
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}
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void DMAChannel::xfer_quad(const DMACmd *cmd_desc, const bool is_store) {
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bool is_writable;
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MapDmaResult res;
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uint8_t *src, *dst;
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uint32_t addr;
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// parse and fix reqCount
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uint32_t xfer_size = cmd_desc->req_count & 7;
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@ -162,22 +177,33 @@ void DMAChannel::xfer_quad(const DMACmd *cmd_desc, const bool is_store) {
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xfer_size = 1;
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}
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// prepare data pointers
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if (is_store) {
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src = mmu_get_dma_mem(this->cmd_ptr, 16, &is_writable);
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src += 8; // move src to cmd.data32
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dst = mmu_get_dma_mem(cmd_desc->address & ~(xfer_size - 1), xfer_size,
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&is_writable);
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} else {
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src = mmu_get_dma_mem(cmd_desc->address & ~(xfer_size - 1), xfer_size,
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&is_writable);
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dst = mmu_get_dma_mem(this->cmd_ptr, 16, &is_writable);
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dst += 8; // move dst to cmd.data32
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}
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addr = cmd_desc->address & ~(xfer_size - 1);
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// perform data transfer only if the destination is writable
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if (is_writable) {
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std::memcpy(dst, src, xfer_size);
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// prepare data pointers and perform data transfer
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if (is_store) {
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res = mmu_map_dma_mem(this->cmd_ptr, 16, false);
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src = res.host_va + 8; // move src to cmd.data32
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res = mmu_map_dma_mem(addr, xfer_size, true);
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if (res.type & RT_MMIO) {
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res.dev_obj->write(res.dev_base, addr - res.dev_base,
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read_mem_rev(src, xfer_size), xfer_size);
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} else if (res.is_writable) {
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std::memcpy(res.host_va, src, xfer_size);
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}
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} else {
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res = mmu_map_dma_mem(this->cmd_ptr, 16, false);
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if (res.is_writable) {
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dst = res.host_va + 8; // move dst to cmd.data32
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res = mmu_map_dma_mem(addr, xfer_size, true);
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if (res.type & RT_MMIO) {
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write_mem_rev(dst,
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res.dev_obj->read(res.dev_base, addr - res.dev_base, xfer_size),
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xfer_size);
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} else {
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std::memcpy(dst, res.host_va, xfer_size);
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}
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}
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}
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if (cmd_desc->cmd_bits & 0xC)
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@ -187,20 +213,20 @@ void DMAChannel::xfer_quad(const DMACmd *cmd_desc, const bool is_store) {
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}
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void DMAChannel::update_irq() {
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bool is_writable;
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// obtain real pointer to the descriptor of the completed command
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uint8_t *cmd_desc = mmu_get_dma_mem(this->cmd_ptr, 16, &is_writable);
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MapDmaResult res = mmu_map_dma_mem(this->cmd_ptr, 16, false);
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uint8_t *cmd_desc = res.host_va;
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// STOP doesn't generate interrupts
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if (this->cur_cmd < DBDMA_Cmd::STOP) {
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// react to cmd.i (interrupt) bits
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if (cmd_desc[2] & 0x30) {
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bool cond = true;
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if ((cmd_desc[2] & 0x30) != 0x30) {
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uint16_t int_mask = this->int_select >> 16;
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cond = (this->ch_stat & int_mask) == (this->int_select & int_mask);
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if ((cmd_desc[2] & 0x30) == 0x20) { // branch if cond cleared?
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cond = !cond;
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if ((cmd_desc[2] & 0x30) == 0x20) {
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cond = !cond; // generate interrupt if cond = false
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}
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}
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if (cond) {
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@ -211,24 +237,22 @@ void DMAChannel::update_irq() {
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}
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uint32_t DMAChannel::reg_read(uint32_t offset, int size) {
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uint32_t res = 0;
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if (size != 4) {
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ABORT_F("DBDMA: non-DWORD read from a DMA channel not supported");
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}
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switch (offset) {
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case DMAReg::CH_CTRL:
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res = 0; // ChannelControl reads as 0 (DBDMA spec 5.5.1, table 74)
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break;
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return 0; // ChannelControl reads as 0 (DBDMA spec 5.5.1, table 74)
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case DMAReg::CH_STAT:
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res = BYTESWAP_32(this->ch_stat);
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break;
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return BYTESWAP_32(this->ch_stat);
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case DMAReg::CMD_PTR_LO:
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return BYTESWAP_32(this->cmd_ptr);
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default:
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LOG_F(WARNING, "Unsupported DMA channel register 0x%X", offset);
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}
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return res;
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return 0;
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}
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void DMAChannel::reg_write(uint32_t offset, uint32_t value, int size) {
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